Chii-Wen Chen

The anomalous behavior of hydrogenated/unhydrogenated polysilicon thin-film transistors under electric stress

The characteristics of high-temperature processed thin-film transistors (TFTs) with/without plasma hydrogenation under the stress condition of V/sub ds/=-15 V and V/sub gs/=0 V have been investigated and compared. It is found that, after stress, the subthreshold swing is greatly improved for unhydrogenated TFTs but not for hydrogenated TFTs. Also, the off-state current is deteriorated for unhydrogenated TFTs but, on the contrary, it is improved for hydrogenated TFTs. A model that takes the effect of hydrogen passivation into account is proposed to interpret the anomalous behavior of TFTs under electric stress.

Improvement on Fluorine Effect under High Field Stress in Tungsten-Polycide Gated Metal-Oxide-Semiconductor Field-Effect Transistor with Oxynitride and/or Reoxidized-Oxynitride Gate Dielectric

Fluorine (F) ions which deduced from tungsten-polycide (W-polycide) formation and affected on metal-oxide-semiconductor (MOS) devices with pure oxide, oxynitride (NO) and re-oxidized oxynitride (ONO) gate dielectric under high field stress were investigated in detail. Although a significant amount of interface states were detected by charge pumping technique in NO and ONO device with W-polycide gate in comparison with that devices with polysilicon gate, however, it is found that NO, and especially ONO gate dielectric, can effectively improve the hot-carrier degradation in W-polycide gated MOS field-effect transistor (FET). This mechanism is well interpreted with a model about F ions increasing the nitrogen concentration at the interface between gate dielectric and Si substrate according to the result of secondary ion mass spectrometry (SIMS) analysis.

To suppress UV damage on the subthreshold characteristic of TFT during hydrogenation for high density TFT SRAM

In this letter, we find an efficient way to suppress UV damage on the characteristics of polysilicon thin-film transistors (TFTs) during hydrogenation for high density TFT SRAM. Polysilicon TFT can be free from UV damage during hydrogenation if the channel region is shielded by a metal line of the same width as channel. After hydrogenation, the metal shielded TFT shows an excellent subthreshold swing of 112 mV/dec, and the leakage current can be as low as 20 fA while the unshielded TFT shows a subthreshold swing of 220 mV/dec and a leakage current of 0.33 pA. This gives almost 200% improvement in subthreshold swing and one order of magnitude reduction in leakage current.

The electrostatic charging damage on the characteristics and reliability of polysilicon thin-film transistors during plasma hydrogenation

In this letter, the impacts of electrostatic charging damage on the characteristics and gate oxide integrity of polysilicon thin-film transistors (TFTs) during plasma hydrogenation were investigated. Hydrogen atoms can passivate trap states in the polysilicon channel, however, plasma processing induced the effect of electrostatic charging damages the gate oxide and the oxide/channel interface. The passivating effect of hydrogen atoms is hence antagonized by the generated interface states. TFTs with different area of antennas were used to study the damages caused by electrostatic field.

Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory

The effects of the substrate bias on the characteristics of split-gate EEPROM/Flash memory cells have been investigated. It is experimentally demonstrated that applying negative substrate bias (NSB) can improve the programming and erasing speed significantly. The improvements can be attributed that NSB effectively increase the needed electrical fields for fast programming and erasing, respectively. Furthermore, the cycling endurance is improved considerably if NSB is applied for programming and erasing operation both.

Rapid thermal annealing on the characteristics of polysilicon thin-film transistors in practical TFT SRAM process

In the practical thin-film transistor (TFT) SRAM process, the rapid thermal contact annealing (RTA) would seriously deteriorate the subthreshold characteristics of TFTs but it can improve the maximum transconductance. We suggest that these degradations are due to the generation of the deep states and we find these degradations can be recovered by a low-temperature anneal in H/sub 2//N/sub 2/ gas ambient.

A novel stack structure to improve the degradation of W-polycide gated MOS device with undoped a-Si/heavily-doped poly-Si multilayer

An original structure with undoped amorphous silicon (a-Si)/heavily-doped polysilicon stacked layers is reported. This structure can help to prevent the deterioration of gate oxide caused by fluorine ions in conventional tungsten-polycide (W-polycide) gated MOS devices. The relationship between the thickness of the stacked a-Si layer and the quality of the gate oxide is also investigated. With this W-silicide/a-Si/polysilicon stack structure, a lower sheet resistance of the W-polycide can also be obtained.

Effects of different tungsten polycide process on the effective channel length and performance of deep submicron CMOS transistors

The effects of different tungsten polycide technologies on the effective channel length and electrical performance of scaled CMOS transistors fabricated by rapid thermal annealing (RTA) have been investigated. Contrary to previous studies, it is found that the sputtered WSi/sub x/ device produces a larger reduction in channel length, a result which is confirmed by gate-to-drain overlap capacitance C/sub GD/ measurement. Experiments also indicate that the sputtered WSi/sub x/ devices possess a lower driving ability, and have higher off state leakage not only for the short channel but also for the long channel range.

Anomalous Current-Voltage Characteristics and Threshold Voltage Shift in Implanted-Polysilicon-Gated Complementary Metal-Oxide-Semiconductor Field-Effect Transistors with/without Titanium-Polycide Technology

The current-voltage (I-V) characteristics and threshold voltage (V t) of implanted-polycrystalline surface channel complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) with and without titanium-polycided polycrystalline silicon gate structures are compared. We find that the earlier punch-through phenomenon is caused by boron (B) penetration into the gate oxide and channel regions in the boron-implanted p+-poly-silicon-gated device, and this degradation is reduced by using titanium-polycide (Ti-polycide) technology. However, this process results in a significant V t shift. In addition, a detailed model for the kinetics of the B redistri-bution and the interface state generation during Ti-salicidation and after post thermal annealing is proposed to explain these phenomena.