Monodeep Kar

Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines

This paper explores fully integrated inductive voltage regulators (FIVR) as a technique to improve the side channel resistance of encryption engines. We propose security aware design modes for low passive FIVR to improve robustness of an encryption-engine against statistical power attacks in time and frequency domain. A Correlation Power Analysis is used to attack a 128-bit AES engine synthesized in 130nm CMOS. The original design requires ~250 Measurements to Disclose (MTD) the 1st byte of key; but with security-aware FIVR, the CPA was unsuccessful even after 20,000 traces. We present a reversibility based threat model for the FIVR-based protection improvement and show the robustness of security aware FIVR against such threat.

Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators

The power attack protection of encryption engines often comes at the expense of area, power, and/or performance overheads making the design of a low-power and compact but secure encryption engine challenging. This paper explores the feasibility of using an on-chip low dropout regulator (LDO) as a countermeasure to power attack of low-power and compact encryption engine. We design an area minimized implementation of Advanced Encryption Standard (AES) using predictive 45nm node and show that lightweight implementations are more susceptible to power attack. Using behavioral modeling, we show that an on-chip LDO can enhance power attack resistance of this compact AES engine; however, the tradeoff between LDO performance and power attack protection is essential. Our analysis shows that LDO can increase power attack resistance of the compact AES by >800X with marginal area (1.4%) and power (5%) overheads.

8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator

Power side-channel attacks (PSCA), e.g. Differential Power Analysis (DPA) and Correlation Power Analysis (CPA), are major threats to the security of crypto engines in SoC platforms. Circuit-level SCA countermeasures to achieve data-independent supply current patterns via implementation of crypto engines using non-conventional logic (complemented [1] or charge recovery [2]) and local switched-capacitor-based supply current equalization [3] have been demonstrated. The feasibility of using bandwidth-limited integrated low dropout regulators, multi-phase switched-capacitor VRs with phase-randomization and integrated inductive voltage regulators (IVR) to enhance PSCA resistance have been explored before via simulation studies [4]. In this paper, we demonstrate improved PSCA resistance offered by an on-die all-digital high-frequency IVR in 130nm CMOS [5] for a standard (unprotected) 128b Advanced Encryption Standard (AES) core designed in static CMOS logic. The IVR features a configurable digital proportional-integral-derivative (PID) controller, a digital discontinuous conduction mode (DCM) controller, and a loop randomization (LR) block, all of which are utilized to enhance PSCA resistance with minimal power/performance/area overheads, while maintaining adequate local voltage regulation and transient performance.

Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study.

This paper shows that inductive integrated voltage regulators (IVR) provide significant immunity to traditional power attacks on crypto encryption engines based on time-domain analysis of the chip current. Frequency-domain analyses of envelope and duty cycle of the current are identified as new attack modes. The security-aware IVR design is discussed to provide additional immunity to power attack.

Integrated all-digital low-dropout regulator as a countermeasure to power attack in encryption engines

Low-drop-out (LDO) voltage regulator modules are being increasingly integrated in the modern processors for efficient power management. This paper shows that an integrated All-Digital LDO (ADLDO) can also be used as a countermeasure against power measurement based side channel attacks. The current transformation introduced by integrated digital LDOs, coupled with the noise due to quantization and limited sampling rate in the control loop, helps suppress the side channel leakage. The ADLDO-based countermeasure is analyzed considering an Advanced Encryption Standard (AES) engine designed in 130nmCMOS. Correlation power analysis and signal-to-noise ratio of the current waveforms at the input of the ADLDO shows significant improvement in power attack resistance over the AES input current.

Impact of process variation in inductive integrated voltage regulator on delay and power of digital circuits

This paper analyzes the effect of variations in the parameters of an Integrated Voltage Regulator (IVR) and its impact on the power/performance of a system of IVR driven digital logic circuit. The coupled analysis of IVR and digital logic considering variations in the integrated passives, power train FETs and controller transistors shows, compared to an off-chip VR, variations in IVR induce much larger shifts in the operating frequency of the logic and total system power. Variations in the output filter passives cause most prominent variations in the system power and performance, particularly pronounced at low voltage operation of the core. We also show that the mean performance of the system can be traded-off to reduce the variability by modifying IVR parameters, such as controller zeroes or output capacitors.

An integrated inductive VR with a 250MHz all-digital multisampled compensator and on-chip auto-tuning of coefficients in 130nm CMOS

This paper presents a bond-wire inductance and on-die capacitance based high-frequency Integrated Voltage Regulator (IVR) with multi-sampled digital controller and all-digital auto tuning engine to tolerate parameter variations of on-die/package-integrated passives. A 130nm CMOS test-chip demonstrates a 125MHz IVR with 250MHz compensator. The auto-tuning shows enhanced performance and stable operation even under ±50% inductance changes. A resistive transient assist (RTA) circuit is presented with up to 2.5x enhancement in transient settling times. A peak efficiency of 71% is measured.

Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering

The paper demonstrates improved power side channel attack (PSCA) resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive voltage regulator (IVR) and all-digital clock modulation (ADCM). The measured power signatures at AES and IVR supply nodes show 9× reduction in peak test vector leakage assessment (TVLA) metric while also protecting encryption keys from correlation power analysis (CPA) attacks even after 500,000 encryption traces.

What does ultra low power requirements mean for side-channel secure cryptography?

The design of low power and side-channel-attack resistant encryption engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel resistance. On one hand, low-power encryption architecture can be more vulnerable to power-attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-attack resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.

(Invited paper) energy delivery for self-powered IoT devices

Distributed small-scale electronics for IoT applications are on the rise. Power delivery for such electronics requires innovative design techniques to improve energy efficiency. This paper summarizes energy delivery challenges for IoT devices and discusses several design techniques for efficient power delivery units. Such design solutions cover challenges like energy harvesting from very low input voltage, maximized energy harvesting, energy delivery with multiple voltage domains and design using low voltage devices to sustain higher than breakdown voltages.