Harish K. Krishnamurthy

A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS

A fully on-die, digitally controlled, 500MHz switching, 250mA rated output buck Voltage Regulator (VR) implemented in 22nm Tri-Gate CMOS is presented. The silicon measured a peak efficiency of 68% and consumed an area of 0.6mm2 (without output decoupling) with a power density of about 410 mW/mm2. The paper also demonstrates a controller bandwidth of 43MHz; the highest reported to date for any digital controller, resulting in output voltage ramp rates as high as 10V/μsec.

Impact of process variation in inductive integrated voltage regulator on delay and power of digital circuits

This paper analyzes the effect of variations in the parameters of an Integrated Voltage Regulator (IVR) and its impact on the power/performance of a system of IVR driven digital logic circuit. The coupled analysis of IVR and digital logic considering variations in the integrated passives, power train FETs and controller transistors shows, compared to an off-chip VR, variations in IVR induce much larger shifts in the operating frequency of the logic and total system power. Variations in the output filter passives cause most prominent variations in the system power and performance, particularly pronounced at low voltage operation of the core. We also show that the mean performance of the system can be traded-off to reduce the variability by modifying IVR parameters, such as controller zeroes or output capacitors.

A digitally controlled fully integrated voltage regulator with 3D-TSV based on-die solenoid inductor with backside planar magnetic core in 14nm tri-gate CMOS

A fully integrated digitally controlled buck VR, featuring hysteretic and PFM control for maximum light load efficiency, with 3D-TSV based on-die solenoid inductor with backside planar magnetic core in 14nm tri-gate CMOS demonstrates 111 nH/mm2 inductance density & 80% conversion efficiency.

Digitally controlled voltage regulator using oscillator-based ADC with fast-transient-response and wide dropout range in 14nm CMOS

In this paper, we propose a digitally controlled voltage regulator with fast-transient-response using an oscillator based ADC implemented in 14nm CMOS technology. The transient response is critical to mitigate droop for large di/dt seen in cores and wide dropout range helps enable DVFS to improve power/performance ratio. In this work, we target 1-1.15V input voltage with output voltage range of 0.5–1.12 V with minimum 30mV dropout, and load current range of >22× with 0.1A–2.2A at 50mV dropout with <0.006mV/mA load regulation using 10-bit power-stage binary control and characterized using a slew-rate programmable synthetic resistive load on-die to mimic core with 18nF load capacitance implemented on-die using area over load.

A digitally controlled linear regulator for per-core wide-range DVFS of atom™ cores in 14nm tri-gate CMOS featuring non-linear control, adaptive gain and code roaming

A digitally controlled LDO in 14nm tri-gate CMOS powering an Atom™ core with embedded power gates enables per-core DVFS over a wide voltage-frequency range. The LDO demonstrates 99.6% peak current efficiency at 2.5A load current and provides a power density of 26.1 W/mm2. The multi-mode digital controller featuring non-linear mode and adaptive gain achieves <20ns settling time with a 100mV droop for a 1.2A load step. A code roaming algorithm complements the feedback controller to successfully mitigate reliability issues from power gate transistor self-heating and electromigration.

Low power all digital acoustic noise suppression technique for switching voltage regulators

An all-digital method of pseudo randomly varying switching frequency of a buck VR in non-linear low power modes (hysteretic and pulse frequency modulation) is proposed in order to reduce acoustic noise. The switching frequency is maintained within the audio range, instead of being increased, and hence switching losses do not increase. The random variation in switching frequency in this scheme converts tonal noise to white noise which has lower peak power and is less noticeable to humans.

A 0.4V∼1V 0.2A/mm 2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS

Monolithic integration of Voltage Regulators (VR) is challenging given the inherent lack of scalability of inductor. Circuit techniques to reduce inductor size are attractive to increase power density and scalability. This paper presents a 70~72% efficient, 500MHz digitally controlled 3-level Buck VR with a fully on-die spiral inductor implemented on 22nm Tri-Gate CMOS with MIM capacitors. The advantages of the 3-level converter for wide range Dynamic Voltage & Frequency Scaling (DVFS) over traditional solutions like linear regulators & Buck VRs are demonstrated.

Synthesizable delay line architectures for digitally controlled voltage regulators

This paper introduces a new architecture for a fully synthesizable digital delay line (DDL) used in digitally controlled voltage regulators. The new architecture uses a variable number of delay elements to lock to the clock frequency depending on the actual process corner and the temperature variations. Also, a comparison between the proposed scheme and the conventional delay line with discretely programmable delay cells is presented. Both schemes are designed using a hardware description language (HDL) and synthesized using Intel 32 nm technology. The comparison shows that the proposed architecture has better linearity, area, and a fast calibration time with respect to conventional delay lines.