Moo-Sung Chae

A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniques

A 1.5-V 512-Mb DDR3 Synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and C IO minimization, which were achieved by on-die-termination (ODT)-merged output drivers, SCR type ESD protection, and self-calibration scheme. The hybrid latency control scheme can turn the DLL off in standby mode, reducing power consumption. User-friendly functions such as temperature read-out from on-chip sensor and per-bank-refresh were also implemented.

Digitally-controlled DLL and I/O circuits for 500 Mb/s/pin /spl times/16 DDR SDRAM

DLL and improved I/O circuits are for 500 Mb/s/pin DDR SDRAM. This digitally-controlled DLL has inherent duty cycle correction capability, enabling fast re-locking upon standby-mode exit. Data input circuits, such as internal delay control and digital sense amplifier, reduce setup/hold window to 0.3 ns. The output data driver has 62% decreased pattern-dependent skew.

A 512 Mbit, 1.6 Gbps/pin DDR3 SDRAM prototype with C/sub 10/ minimization and self-calibration techniques

A 1.5 V, 512 Mbit DDR3 synchronous DRAM prototype with 1.6 Gbps/pin was designed in 80nm technology. Output drivers are merged with ODT and are armed with SCR type ESD protection, rendering C/sub 10/ minimization for the enhanced signal integrity in point-to-2points interfacing. Hybrid latency control scheme is proposed to achieve higher bandwidth as well as to efficiently turn DLL on and off. Temperature readout and per-bank-refresh is also implemented.