Moon Gi Seok

Interoperation between Engagement-and Engineering-level Models for Effectiveness Analyses

System effectiveness analyses are a longstanding challenge in defense modeling and simulation. While some techniques are accomplished through using an engagement-level model alone with given parameterized weapon performance data, this approach is prone to errors because of insufficient behavior information from the weapon systems. In order to overcome these limitations, engagement-level models should be supported by engineering-level models representing the detailed behavior of weapons. Hence, this paper proposes an interoperation approach between the engagement and engineering-level models. Our approach produces meaningful results in terms of various engagement tactic alternatives for the suitable performance of weapons under given situations, such as operational environments, operational errors, and so on. The proposed method is demonstrated through an anti-torpedo combat simulation, including the engagement and the engineering-level models. We perform experiments by varying tactical military scenarios or performance indices of decoy systems. Experimental results show suggestions for operational tactics and weapons specifications in order to meet requirements.System effectiveness analyses are a longstanding challenge in defense modeling and simulation. While some techniques are accomplished through using an engagement-level model alone with given parameterized weapon performance data, this approach is prone to errors because of insufficient behavior information from the weapon systems. In order to overcome these limitations, engagement-level models should be supported by engineering-level models representing the detailed behavior of weapons. Hence, this paper proposes an interoperation approach between the engagement and engineering-level models. Our approach produces meaningful results in terms of various engagement tactic alternatives for the suitable performance of weapons under given situations, such as operational environments, operational errors, and so on. The proposed method is demonstrated through an anti-torpedo combat simulation, including the engagement and the engineering-level models. We perform experiments by varying tactical military scenarios or performance indices of decoy systems. Experimental results show suggestions for operational tactics and weapons specifications in order to meet requirements.

Hierarchical Federation Composition for Information Hiding in HLA-Based Distributed Simulation

This paper presents a hierarchical federation system interconnected among federations and proposes a hierarchical federation composition algorithm that composes federations into different compositions of hierarchical federations and then efficiently assigns composite federations to a distributed environment while enabling information hiding. We implement the hierarchical federation system and evaluate it using real networks. The experimental results show that our composition algorithm performs better than a random composition algorithm in optimizing the composition of federations while achieving information hiding.

An HLA-Based Distributed Cosimulation Framework in Mixed-Signal System-on-Chip Design

In mixed-signal system-on-chip (SoC) design, distributed cosimulation is one of the practical approaches for unifying various abstracted hardware models using different description languages. Conventional ad hoc distributed cosimulation solutions do not have formal theoretical backgrounds of simulator integration into their solutions. In this brief, we propose a general cosimulation framework based on the high-level architecture (HLA) and newly defined programming language interface for interoperation (PLI-I) as a formal simulator interface. Based on the PLI-I and HLA, we propose formal integration and interoperation procedures. To reduce integration costs, the procedures have been developed into a common library and then merged with model-dependent signal-event converter to handle differently abstracted in/out signals. During the interoperation, to resolve the different time-advance mechanisms of the digital and analog simulators, the adapter executes an advanced HLA-based synchronization based on the presimulation concepts. The case study shows the reduced design effort in integrating and validating the heterogeneous models and simulators using the proposed framework in mixed-signal SoC design.

Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability

Designing a mixed-signal integrated hardware requires the mixed simulation for legacy digital blocks and analog circuits, which are usually represented by the Verilog description language for digital blocks and the SPICE circuit netlist of analog circuits. Without model translations or source-level modifications and to simulate mixed legacy Verilog models and SPICE circuit netlists that are usually developed based on the different SPICE languages, parameters and primitives, this paper proposes a simulation framework whose concept is connecting a legacy Verilog and proper SPICE simulator for the target SPICE model using a run-time infrastructure (RTI) based on high level architecture (HLA) and adapters that are pluggable libraries to enable the interoperation and integration of simulators through HLA. For the interoperation, to exchange analog/digital signals, the adapter converts analog/digital signals to events or events to analog/digital signals using user-defined, signal-event converters. To synchronize different time advance policies, the adapter performs time synchronization procedures based on the pre-simulation concept. For the integration of Verilog/SPICE simulators and the RTI, adapters are developed following each component interface, which are IEEE-std Verilog procedural interface, proposed SPICE procedural interface and IEEE-std HLA interface. The proposed framework was applied to the digitally controlled buck converter simulation.

A Scalable Modeling and Simulation Environment for Chemical Gas Emergencies

To reflect an evacuation process using a conventional agent-based approach to model human movement under chemical gas exposure, a scalable and hybrid agent-based simulation (ABS) model incorporates an interactive computational fluid dynamics (CFD) gas flow model. To embrace the hybrid ABS model, CFD model, and models for countermeasure in various domains, a scalable runtime infrastructure (RTI)-based simulation environment is also proposed. This environment provides a simulator-level interface to integrate a continuous and discrete-event simulator into the RTI by resolving data/event interaction and time synchronization among heterogeneous simulation models. The authors successfully interoperated the hybrid ABS model, interactive CFD model, control center model, and gas sensor model to evaluate the countermeasures in the proposed environment. As a case study, they applied a 3D-based virtual training engine as a standalone modeling and simulation element to show the scalability of the proposed environment.

Maximum Stack Memory Monitoring Method Assisted by Static Analysis of the Stack Usage Profile

As IoT permeates through industry in general, the safety assurances of IoT will become a major issue. One of the major safety issues, stack overflow, is a bothersome and difficult problem because it is hard to discover during design and to prevent. Many related studies for preventing stack overflow have used two general methods. The static analysis method is employed before a program runs and estimates the program’s probable maximum stack memory usage. The dynamic analysis method is used to monitor for stack overflows during run-time. Based on those prior works, this paper introduces a method for monitoring stack memory based on static analysis of the maximum stack memory usage profile. We anticipate that applying the proposed approach will prevent stack overflow in an efficient manner.

Automatic on-chip backup clock changer for protecting abnormal MCU operations in unsafe clock frequency

Mission-critical MCU-based systems under severe electrical situations cause malfunctioning by the disturbance in the clock path. MCU-based systems in clockless status loses their contrability in high-current output or glitch-clock injection may destroy status value of flip-flops. In this paper, we propose the automatic clock failure detection and protection by implementing a fully synthesizable edge detector, noise canceller logic and glitch-free clock changer circuit. To determine several noise-vulnerable data/clock paths, we propose a presimulation framework to reconstruct a clock noise propagation path from the entire circuit netlist. We successfully increased the noise immunity characteristics by allocating the detector units into efficient locations.