Morteza Vadipour

Capacitive feedback technique for wide-band amplifiers

A bandwidth-enhancing technique is presented for wideband amplifiers. In this technique a capacitive feedback scheme is used in analogy to resistive feedback amplifiers. As capacitive feedback does not lower gain, the technique does not trade off gain for bandwidth. Computer simulations and practical circuits show a considerable improvement over the conventional widebanding techniques. >

A 2.1mW/3.2mW delay-compensated GSM/WCDMA ΣΔ analog-digital converter

A technique to compensate for the harmful excess loop delay in a continuous time SigmaDelta analog-digital converter is presented. With no extra power consumption or area penalty the technique is suitable for variety of applications employing continuous time SigmaDelta analog-digital converters. This work presents a dual mode SigmaDelta ADC for GSM/WCDMA applications with DR of 86 dB/63 dB for 100 KHz/1.92 MHz in a 65 nm CMOS technology with power consumption of 2.1 mW/3.2 mW.

A quad-band GSM/GPRS/EDGE SoC in 65nm CMOS

A quad-band 2.5G SoC integrates all the RF, DSP, ARM, audio and other baseband processing functions into a single 65nm CMOS die. The radio draws a battery current of 49mA in the RX-mode, and 86mA in the GMSK TX-mode. The low-IF receiver achieves a sensitivity of −110dBm at the antenna, corresponding to a noise figure of 2.4dB at the device input. The 8PSK ±400kHz modulation mask is −64.1/62.7dBc for high/low bands, with an RMS EVM of 2.45/1.95%.

A Quad-Band GSM/GPRS/EDGE SoC in 65 nm CMOS

A quad-band 2.5G SoC integrating all the RF, DSP, ARM, audio and other baseband processing functions into a single 65 nm CMOS die is described. The paper focuses on the radio portion mostly, and addresses the challenges of realizing a complete GSM/EDGE SoC with the RF integrated along with the rest of digital baseband circuitry. Several circuit level as well as architectural techniques are presented to realize a very low-cost and low-power 2.5G radio while meeting the stringent cellular requirements with wide margin. The radio draws a battery current of 49 mA in the receiver-mode, and 86/77 mA in the GMSK/8PSK transmit-mode. The low-IF receiver achieves a sensitivity of -110 dBm at the antenna, corresponding to a noise figure of 2.4 dB at the device input. The 8PSK±400 kHz modulation mask is - 64.1/62.7 dBc for high/low bands, with an RMS EVM of 2.45/1.95%. The radio core area is 3.95 mm2 .

A Differential Digitally Controlled Crystal Oscillator With a 14-Bit Tuning Resolution and Sine Wave Outputs for Cellular Applications

This paper describes the design topologies and considerations of a differential sinusoidal-output digitally controlled crystal oscillator (DCXO) intended for use in cellular applications. The oscillator has a fine-tuning range of ±44 ppm, approximately 14 bits of resolution, and an average step size of 0.005 ppm. All signals connecting externally to I/O pins are sine waves for reducing noise, interference, and spurs couplings. The 26 MHz DCXO fabricated in 65 nm CMOS achieves a phase noise of -149.1 dBc/Hz at 10 kHz offset measured at the sine wave buffer output. The DCXO is capable of meeting the stringent phase noise requirements for IEEE 802.11n 5 GHz WLAN devices. A typical frequency pulling of 0.01 ppm due to turning on/off the sine wave buffer is measured. The DCXO dissipates 1.2 mA of current, whereas each sine wave output buffer draws 1.4 mA. The DXCO occupies a total silicon area of 0.15 mm2 .

A Rel-12 2G/3G/LTE-Advanced 3CC Cellular Receiver

This work presents a receiver capable of receiving three simultaneous cellular channels with an aggregate bandwidth of 60 MHz, enabling a 300 Mb/s downlink rate. The receiver has 16 RF LNA ports covering the cellular bands within the 572-2700 MHz frequency range. It supports LTE-advanced Rel-12 Cat6, HSPA+ Rel-11, TD-SCDMA Rel-9, and GSM/EDGE Rel-9. The 40 nm CMOS receiver consumes 13.7 and 17.6 mA of battery current in 3G and LTE modes, respectively, including the PLL, DCXO, and biasing for a single channel.

A new compensation technique for resistive level shifters

A compensation technique is introduced for resistive level-shifting stages that reduces the size of the compensating capacitor from 20-30 pF in conventional compensation to about 2-3 pF, making the stage more attractive for use in many analog ICs such as op amps, comparators, and wideband amplifiers. >

A Rel-12 2G/3G/LTE-advanced 3CC receiver

This work presents a cellular receiver capable of receiving three simultaneous channels with an aggregate bandwidth of 60 MHz, enabling a 300 Mbps downlink rate. The receiver has 16 RF LNA ports covering the cellular bands within the 572-2700 MHz frequency range. It supports LTE-advanced Rel-12 Cat6, HSPA+ Rel-11, TD-SCDMA Rel-9, and GSM/EDGE Rel-9. The 40 nm CMOS receiver consumes 13.7 mA and 17.6 mA of battery current in 3G and LTE modes, respectively, including the PLL, DCXO, and bia sing for a single channel.

A temperature compensated VCO using feed-forward gain multiplication for cellular applications

A new LC-tank VCO to minimize frequency drift due to temperature variations for cellular applications is presented. By employing the feed-forward VCO gain multiplication technique, frequency drift is reduced by 83% without resorting to conventional temperature dependent biases and circuits. Additionally, the compensation circuit retains the original VCO behavior with no degradation in performance. A fractional-N PLL fabricated in 40 nm CMOS shows that the VCO draws 9 mA and the temperature compensation circuit draws 200 μA. Measurements show that the VCO has a tuning range of 46% (from 2890 MHz to 4560 MHz) and a phase noise of -102 dBc/Hz at 200 kHz offset centered at 3960 MHz at the PLL output before the divide-by-two circuit for 3G/LTE Band I.

Optimum degeneration for minimum mismatch in bipolar current sources

Statistical analysis of mismatch in bipolar degenerated current sources reveals the existence of an optimum degeneration for minimum mismatch. Extra degeneration does not improve matching but degrades it and forces unnecessary DC restrictions on the circuit. >