Motoaki Tani

Integrated module structure of fan-out wafer level package for terahertz antenna

We propose a novel integrated antenna module based on fan-out wafer level package (FO-WLP) for terahertz applications. A patch structure is employed for an antenna since it is suited for low height module. Both an insulator made of polyphenylene ether (PPE) and a reflector made of copper block, together with a chip for high frequency operation, were embedded into a mold used for FO-WLP. A driven element of the antenna and an interconnection between the antenna and the chip were formed by redistribution layer (RDL) technology. The height of the insulator was set to 40 um in order to maximize the radiation efficiency of 300-GHz radio wave. We developed the module and evaluated the performances. Measured frequency characteristics were well matched to analytical result. The measured loss of reflection characteristics of developed module was 3 dB. Therefore, the module achieved 1.5-dB insertion loss even at terahertz frequency. These results exhibit proposing structure is effective as a terahertz module.

Simulation of differential skew considering fiber kink effects

As a result of increasing signal transmission rates to as high band levels as several tens of Gbps, skew induced by the difference in dielectric constant between the glass-cloth and the resin is posing a huge problem. However, due to the extremely difficult comparison of this skew between actual measurements and simulations, few studies on such comparison have been reported to date. We developed a new analysis technique to clarify the transmission delay time difference (skew) in differential signal transmission lines, depending on the positional relationship between the glass-threads and the conductor lines in a circuit board. This analysis technique has the following four characteristics. The first is that the angle of the lines to the glass-cloth is expressed by cascade connections of multiple analytical models that are different in the positional relationship between the glass-cloth and the lines. The second is that analytical models are combined in cascade connection assuming that the positional relationship between the lines and the glass-cloth appears randomly and is distributed uniformly. The third is that analytical models are prepared assuming that the angle between the lines and the glass-cloth is distributed uniformly within a certain range due to fiber kink effects. The fourth is that the assumption that skew in stripline structure, which has two glass-cloth insulating layers right above and below the lines, can be calculated by the sum of two sets of the skew induced by one glass-cloth-containing insulating layer. As a result of comparison between analysis and actual measurement results, it was confirmed that this analysis technique could reproduce skew distributions observed in real circuit boards with a high degree of accuracy.As a result of comparison between analysis and actual measurement results, it was confirmed that this analysis technique could reproduce skew distributions observed in real circuit boards with a high degree of accuracy.

The effect of surface roughness on high frequency transmission line

We propose a method for measuring effects of surface roughness on transmission characteristics eliminating the manufacturing error. We verified the structure using electromagnetic simulation and measured three different types of surface roughness.

A 77 GHz CMOS power amplifier module using multi-layered redistribution layer technology

This paper presents a new millimeter-wave module concept, which is an integration of CMOS monolithic microwave integrated circuits (MMICs) and passive devices fabricated using a redistribution layer (RDL) technology. To realize a low-loss passive circuit, we introduced a multi-metal-layer for the RDL. The first metal layer was used as ground to shield from substrates. The upper metal layers form passive RF components such as a thin film microstrip line (TFMSL), a spiral inductor, a balun, a power combiner, and an antenna. Detailed measurements and characterizations are presented, and we show their applicability in the millimeter-wave region. Moreover, this concept was applied to an integrating millimeter-wave module consisting of four identical CMOS power amplifiers and RDL power combiners to increase the output power. The module exhibited a saturation power of 15 dBm, which is almost four-times higher than that obtained from the single PA. The measured small-signal gain of the PA module was 5.4 dB. The total chip size was 2.2 × 1.5 mm2. The power consumption of the PA module was 800 mW.

Measurement of high-frequency conductivity affected by conductor surface roughness using dielectric rod resonator method

In recent years, high-end interconnects have enabled signal transmission rates of tens of gigabits per second (Gbps) in printed circuit boards (PCB). Reducing the transmission losses induced by conductor surface roughness in a PCB is important from the standpoint of signal integrity. In this study, we measured the effects of surface roughness in a PCB using a dielectric rod resonator method. Then, we derived a relative power dissipation Ksr approximation from the measurement results for the firs time. The dielectric rod resonator method makes it possible to measure only the effects of surface roughness because conductivity is analyzed in a characteristics equation using TE0mn (m; n is the integer) modes which the dielectric rod does not influence The results showed that the Ksr factor was seven times greater than that of the smooth surface. This result is higher than the previous results of measuring the effects of surface roughness. We applied the measurement results to the Ksr approximation equation and verifie the transmission line of a microstrip. We confirme that the insertion loss of the transmission line was successfully measured and simulated. This method can be applied to any copper wiring in a PCB because it can include not only the effects of surface profil but also the effects of a surface treatment agent.

Electrical characteristics of build-up substrates using new via structures

The electrical characteristics of the power supply path, which are influenced by the via structures in the build-up substrate were investigated. The build-up substrates are composed of core layers and build-up layers, connected by the plated through hole (PTH), and the build-up via (BU via), respectively. This paper investigates how the BU via structures affect the power supply path, and discusses the design constraints of the via structures in the build-up layers. Three design constraints were considered for the build-up substrate, which comprises six build-up layers laminated on both sides of the core layers. The first constraint limits the BU via stack number, the second is the propriety of the BU via stack on the PTH, and the last limits the number of BU vias connected on the PTH. By changing these design constraints, the power supply paths were designed and compared by simulation and measurement. As a result, the proposed via structure significantly reduced the resistance and inductance of the power supply path in the substrate, while yielding good connectivity and productivity.