Shoichi Miyahara

Thermal stress reliability of copper through silicon via interconnects for 3D logic devices

For 3D-LSI devices using the through silicon via (TSV) process, there are many reliability issues regarding the large thermal-mechanical stress and deformation volume changes caused by mismatch of the thermal expansion coefficients (CTEs) between the Cu and Si substrate in the device active area. In this paper, we investigated the TSV leakage current in metal-insulator-semiconductors and studies MOSFET device characteristics to manage manufacturing quality based on stress propagation of Cu-TSVs by thermal loading in the operating temperature range (−50 to 80 °C) and relatively high process temperature range (250 to 400 °C). The stress induced leakage current and MOSFET mobility change showed a relationship between expansion and contraction deformation of Cu under the thermal loading conditions. These results show that Cu/Si interface formation quality is high although there is major TSV metallization. Furthermore, it was found that precise estimation is important to designing the keep out zone (KOZ) in consideration of the real operating temperature.

Study of MOSFET thermal stability with TSV in operation temperature using novel 3D-LSI stress analysis

A large thermal-mechanical stress caused by the mismatch of thermal expansion coefficients (CTEs) between the copper and silicon substrate occurs in the active area of the stacked 3D device using the through-silicon via (TSV). Therefore, the study of TSV-induced stress is of fundamental importance in our understanding of the keep-out zone (KOZ). We investigated the metal-oxide-semiconductor field-effect transistor (MOSFET) thermal stability of a device operated by combining Technology Computer-Aided Design — Simulation Program with Integrated Circuit Emphasis (TCAD-SPICE) stress analysis and an actual ring oscillator circuit (ROSC) nearby TSVs. The MOSFET drain current (Id) fluctuates in response to the behavior of the Si stress caused by the TSVs. However, it was found that the simulation and test measurement results showed that the KOZ becomes smaller because the electric charge/discharge is canceled in the case of a p/n MOS inverter circuit. This study showed the importance of the design of the KOZ, which includes the temperature fluctuation phenomenon in a real integrated circuit device operation.