Daisuke Mizutani

Low warpage coreless substrate for large-size LSI packages

Due to inadequate rigidity, warpage of coreless substrates is generally large compared to other types of LSI package substrates. Therefore, the most important problem in the application of coreless substrates is warpage reduction during the reflow process. So far, there have been only a limited number of reports on coreless substrates for large-size LSI packages. Moreover, there have been very few examples that discussed substrate layer structure designs for warpage reduction and reliability improvement in the LSI assembly process. In the present study, we focus on developing coreless packages for large-size LSIs. To achieve our goal, we adopted the following development processes. First, we designed analytical models with different layer structures comprising two kinds of materials, and investigated the effect of layer structure on warpage reduction using warpage simulations. Next, we made four kinds of real coreless substrates with layer structures identical to the simulation models, and verified the actual thermal warpage behavior. Finally, we investigated the thermal stress reliabilities of these substrates after LSI mounting. From the results, we found that warpage reduction and reliability enhancement of coreless substrates were realized by arranging the high rigidity materials on the external layers of the substrates.

Characterization of signal via structure in multilayer printed circuit boards up to 50 GHz

Interconnects in the latest servers need a transmission capability of tens of gigabits per second (Gbps) for high-speed digital circuits. For the system board in servers, the impact of losses in through-hole vias on the performance is large in the region of tens of Gbps. In this paper, we discuss the capability of 100 Gbps electrical signal transmission in typical through-hole vias in a system board. After the simulation model and the simulation results are validated by measurements, the causes of losses are analyzed in detail on the basis of the simulations. Consequently, it is confirmed that the reflection and the radiation losses are dominant. To reduce the reflection and radiation losses, we investigate the signal via structures and ground and differential via structures, respectively. As a result, it is clarified that these losses can be reduced by designing the above mentioned structures appropriately.

Precision improvement study of thermal warpage prediction technology for LSI packages

A finer interconnection pitch of LSI packages has enhanced the importance of precise prediction technology of temperature-dependent warpage. In our research, we prepared a model package with minute wiring and vias, and examined a method of improving the agreement accuracy between numerical analysis and measurement of temperature-dependent warpage. To improve the precision of warpage prediction technology, we paid attention to warpage measurement technology, especially the temperature distribution in a sample, in addition to improving the accuracy of the numerical analysis model and material properties. We succeeded in heating a substrate with a temperature difference of 20°C or 3°C between the top side and bottom side, by controlling the heating conditions. Furthermore, the numerical analysis with a fine wiring model was performed under conditions where the temperature varied in consideration of the thermal conductivity of the substrate. The material properties for the numerical analysis, such as Coefficient of Thermal Expansion and Relaxation Modulus were measured very carefully with original setups, because they are essential for improving the accuracy of our numerical analysis. As a result, we found that substrate warpage with an uneven temperature distribution is quite different from such warpage with uniform temperature. To predict the temperature-dependent warpage with a high accuracy, we found that the temperature distribution in a substrate should be considered in the numerical analysis, besides applying the precise model and material properties.

Development of second-level connection method for large-size CPU package

This paper reports on second-level interconnection development for a large-scale Ball Grid Array (BGA) package. Generally, control of warpage becomes a problem as BGA packages become larger. To solve this problem, the following two measures were executed. The first was adoption of a low-temperature solder, and the second was warpage control using a heat spreader as a fixture. We were able to decrease the reflow temperature to 200°C by applying the low-temperature solder, and the effect was a warp reduction of 200 μm. Moreover, the shape of the heat spreader was optimized through a thermal-stress simulation, obtaining a warp reduction of 100 μm. Verification with a test vehicle was executed, no short/opening was observed, and the results of a thermal cycle test and simulation confirmed there was no problem in reliability.

Development of CPU Package Embedded with Multilayer Thin Film Capacitor for Stabilization of Power Supply

This paper proposes a method of improving power delivery in a CPU package substrate with multilayer thin film capacitors (TFCs). Because TFC embedded technology can reduce the inductance of power delivery path, it can stabilize the power supply to the CPU. Higher permittivity, thinner layer thickness and wider conductor plane area results in larger capacitance. To further stabilize the power supply, we developed a package structure with an embedded double TFC layer that can double the capacitance. The double TFC embedded package was formed by laminating two TFCs to the top and bottom of the core layers in a build–up substrate. Through verification using test vehicles, it was confirmed that electrical performance was significantly improved with the double TFC. Also, it was demonstrated that the criteria of the capacitance and insulation resistance were satisfied in the product reliability tests.

Simulation of differential skew considering fiber kink effects

As a result of increasing signal transmission rates to as high band levels as several tens of Gbps, skew induced by the difference in dielectric constant between the glass-cloth and the resin is posing a huge problem. However, due to the extremely difficult comparison of this skew between actual measurements and simulations, few studies on such comparison have been reported to date. We developed a new analysis technique to clarify the transmission delay time difference (skew) in differential signal transmission lines, depending on the positional relationship between the glass-threads and the conductor lines in a circuit board. This analysis technique has the following four characteristics. The first is that the angle of the lines to the glass-cloth is expressed by cascade connections of multiple analytical models that are different in the positional relationship between the glass-cloth and the lines. The second is that analytical models are combined in cascade connection assuming that the positional relationship between the lines and the glass-cloth appears randomly and is distributed uniformly. The third is that analytical models are prepared assuming that the angle between the lines and the glass-cloth is distributed uniformly within a certain range due to fiber kink effects. The fourth is that the assumption that skew in stripline structure, which has two glass-cloth insulating layers right above and below the lines, can be calculated by the sum of two sets of the skew induced by one glass-cloth-containing insulating layer. As a result of comparison between analysis and actual measurement results, it was confirmed that this analysis technique could reproduce skew distributions observed in real circuit boards with a high degree of accuracy.As a result of comparison between analysis and actual measurement results, it was confirmed that this analysis technique could reproduce skew distributions observed in real circuit boards with a high degree of accuracy.

The effect of surface roughness on high frequency transmission line

We propose a method for measuring effects of surface roughness on transmission characteristics eliminating the manufacturing error. We verified the structure using electromagnetic simulation and measured three different types of surface roughness.

Development of Large Size CPU Package Structure Using Embedded Thin Film Capacitor Package Substrate

This paper reports on a large-size CPU package for UNIX servers which employs embedded thin film capacitor layers. The substrate of this package has two thin film capacitor layers in the surface of the core layer, which has a capacitance of 25 uF in total. In order to adopt this package substrate, we confirmed the effect of the thin film capacitor layers on the package assembly process. We actually measured mechanical characteristics and the coefficient of thermal expansion (CTE), and confirmed that we can use it like conventional package substrates. This package has passed the preprocessing and subsequent environmental test on JEDEC Level 4, and we think that a high-quality package has been developed this time. Fujitsu adopted a low melting point solder BGA from a previous-generation package. Its composition is Sn-57Bi-1.0Ag. However, this solder has an issue with deformation after a low-temperature reflow profile for the solder ball attachment process on the package. In this work, we were able to find the cause of this phenomenon, and by changing the Ag content from 1.0% to 0.4%, we achieved a complete low-temperature assembly process. In addition, BGA connection reliability was confirmed.

Viscoelastic analysis of multistage stacked via structure in build-up substrate

Compact high density electronic equipment is achieved using the stacked via technology in a build-up substrate. In order to design the build-up substrate, the impact of the viscoelasticity behavior of insulating resin under heating and cooling must be considered. This paper investigates how to predict the stacked via fatigue life using a viscoelastic analysis. The thermal cycle test, elastic analysis and the viscoelastic analysis were conducted in eight variations of stacked via structure including either of two resins. Either three, four, five, or six build-up via (BU via) were stacked on the plated-through hole (PTH) in these structures. As a result, the viscoelastic analysis agreed well with that of the thermal cycle test in any stacked via structure.

Measurement of high-frequency conductivity affected by conductor surface roughness using dielectric rod resonator method

In recent years, high-end interconnects have enabled signal transmission rates of tens of gigabits per second (Gbps) in printed circuit boards (PCB). Reducing the transmission losses induced by conductor surface roughness in a PCB is important from the standpoint of signal integrity. In this study, we measured the effects of surface roughness in a PCB using a dielectric rod resonator method. Then, we derived a relative power dissipation Ksr approximation from the measurement results for the firs time. The dielectric rod resonator method makes it possible to measure only the effects of surface roughness because conductivity is analyzed in a characteristics equation using TE0mn (m; n is the integer) modes which the dielectric rod does not influence The results showed that the Ksr factor was seven times greater than that of the smooth surface. This result is higher than the previous results of measuring the effects of surface roughness. We applied the measurement results to the Ksr approximation equation and verifie the transmission line of a microstrip. We confirme that the insertion loss of the transmission line was successfully measured and simulated. This method can be applied to any copper wiring in a PCB because it can include not only the effects of surface profil but also the effects of a surface treatment agent.