Motoshige Igarashi

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mum2 SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology

A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits

We propose a new design scheme to improve the SRAM read and write operation margins in the presence of a large Vth variability. By applying this scheme to a 0.494 mum2 SRAM cell with a beta ratio of 1, which is an aggressively small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth value using a 65 nm LSTP CMOS technology

Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45 nm Node Devices and Beyond

In this paper, a novel shallow trench isolation (STI) process is proposed for 45 nm node technologies and beyond. The major features of this process are the use of a fluorine-doped (F-doped) SiO2 film for gap filling and high-temperature rapid thermal oxidation (HT-RTO) for gate oxidation. Voidless filling of a narrow trench can be realized by F-doped high-density plasma chemical vapor deposition (F-doped HDP-CVD). Moreover, electron mobility degradation caused by STI stress and junction leakage currents can be minimized using F-doped HDP-CVD with HT-RTO. It was also confirmed that compressive stress in the F-doped HDP-CVD sample is smaller in every measurement point around STI than that in the conventional HDP-CVD sample by convergent-beam electron diffraction (CBED). The Si-F bonds in the oxide film play a very important role in stress reduction. By utilizing HT-RTO, Si-F bonds remain and make the SiO2 film in the trench coarse. This technique is a very promising 45 nm node STI scheme with high performance and high reliability.

A 65 nm Ultra-High-Density Dual-Port SRAM with 0.71um/sup ~/ 8T-Cell for SoC

We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71mum2 8T-DP-cell, which cell size is 1.44times larger than 6T-single-port (SP) cell

A Large Scale, Flip-Flop RAM imitating a logic LSI for fast development of process technology

We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.

A dynamic body-biased SRAM with asymmetric halo implant MOSFETs

In this paper, we propose an SRAM macro that realizes 0.5V operation by combining a device technique with simple design architecture. Regarding the device technique, we utilize asymmetric halo implant MOSFETs, which enables to enhance both the static noise margin and write margin of SRAM, simultaneously. As for the design technique, dynamic body-bias scheme which operates body bias dynamically is introduced to overcome the speed degradation due to lower supply voltage. Showing measured data fabricated on 45nm CMOS technology, we demonstrate a plausible scenario for achieving 0.5V operating SoC products.

Improving SRAM read/write margin with asymmetric halo MOSFET

We propose SRAM bitcells with asymmetric halo implant dose MOSFET (AH-MOS) by introducing additional masks for halo implant steps. AH-MOS has different drain-source currents (Ids) between forward and reverse directions (Fig. 1). By implanting high and low dose for drain and source regions respectively, Ids flowing from drain to source (forward) gets larger than that from source to drain (reverse). Fig. 2 shows 6T SRAM bitcell with AH-MOS [1]. The current at pass-gate (PG), which consists of AH-MOS, flows bi-directionally in read and write mode. The pull-down (PD) is symmetric halo implant dose MOSFET (SH-MOS) due to unidirectional currents. The pull-up (PU) is also SH-MOS.

A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology

We have developed a power-gating technique for a mobile processor in 28-nm HKMG technology. The proposed EM-tolerant 1.8V I/O NMOS power switch reduces the standby power to 1/641× and achieves 79% channel utilization without weakening EM immunity. The active leakage power of the dual CPU cores can be reduced by 45 mW in a single core operation mode with a rapid 1.4-μs wakeup time to full core operation. A mobile processor is designed and fabricated with proposed technique. Estimated standby power of the chip is 123 μW, resulting in one order of magnitude reduction compared to the conventional techniques. Measured leakage power shows a good agreement with the estimated one.

A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology

We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.