M. Inuishi

A 1 V 46 ns 16 Mb SOI-DRAM with body control technique

Low-voltage and low-power DRAMs of appropriate capacity are required for portable systems such as portable PCs and Personal Digital Assistants (PDAs). Though a 1.2 V 49 ns bulk-DRAM has been reported, still lower voltage operation is difficult for bulk-DRAMs, due to the back bias effect and large junction capacitance. SOI devices have several advantages over bulk devices, such as small subthreshold swing (S-factor), elimination of the back bias effect, and small junction capacitance. To utilize these advantages, many SOI-DRAM studies and proposals have been made. The basic operation of the SOI-DRAM at 2.3 V has been examined using an experimental 64 kb SOI-DRAM, and a 3 V 50 ns 16 Mb SOI-DRAM has been also reported. Here the authors present a 1 V 46 ns 16 Mb SOI-DRAM which uses a 0.5 /spl mu/m CMOS/SIMOX process. To accelerate low-voltage speed, a body-pulsed sense amplifier (BPS) and body-driven equalizer (BDEQ) are used. The conventional body-control technique uses partially-depleted (PD) transistors. In contrast, fully-depleted (FD) transistors are used to reduce leakage current in the off-state.

Impact of actively body-bias controlled (ABC) SOI SRAM by using direct body contact technology for low-voltage application

Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure including connections of the access and the driver transistors bodies to the word line is proposed to realize low-voltage operation. We developed the direct body contact technology to apply forward biases to the bodies without area penalties and increases of parasitic gate capacitances by using the hybrid trench isolation for the first time. Moreover, the standby current does not change because the body bias is not applied when the word-line voltage is low level. It is successfully demonstrated that low-voltage and high-speed operation is achieved by using the ABC SOI SRAM.

Impact of 0.10 /spl mu/m SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 /spl mu/m era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-relate speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk structure. Moreover, it is shown that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSIs. It is concluded that SOI technology with HTI structure is one of the solutions against the scaling limitations.

Proximity gettering of heavy metals by high-energy ion implantation

We studied the proximity gettering of heavy metals by secondary defects, using high-energy, high-dose ion implantation by means of intentional contamination of samples with copper and iron. It was demonstrated that the secondary defects induced by high-energy boron or silicon implantation can act as gettering sites of heavy metals and reduce the junction leakage current. Proximity gettering by silicon implantation is found to be more effective than that by boron implantation. Moreover it is found to be difficult to getter iron atoms in comparison with copper atoms.

Application of nitrogen implantation to ULSI

Abstract Nitrogen is not a commonly used ion species in Si ULSI. It cannot be used as an n-type dopant because of its low solubility in Si. However, it shows interesting properties such as the suppression of boron diffusion when applied to source/drain doping and the nitridation of gate oxide when applied to gate doping. In this report, first, the effects of nitrogen preimplantation to the formation of boron-doped shallow p+n junctions are described. The technique is successfully applied to 0.25 μm PMOSFETs, forming shallow junctions and thus suppressing short channel effects. Next, the effects of nitrogen implantation into p+ poly-Si gates are studied. The implanted nitrogen diffuses to the gate oxide during annealing and nitrides the gate oxide. As a result, boron penetration through the gate oxide is suppressed and the reliability and hot carrier resistance are improved.

16 Mb DRAM/SOI technologies for sub-1 V operation

Extra low voltage DRAM/SOI technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFETs, and (4) reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16 MDRAM/SOI was successfully realized and functional operation was obtained at very low supply voltage below 1 V.

Bulk-layout-compatible 0.18 /spl mu/m SOI-CMOS technology using body-fixed partial trench isolation (PTI)

Transistor performance improvement has been strongly required for work toward highly integrated intelligent system LSIs. To meet this demand, silicon on insulator (SOI) has become of major interest for next generation devices, because it can offer durable device scaling as compared with bulk devices (Schepis et al. 1997). The critical issues for SOI are floating-body effects such as deterioration in drain current (Matsumoto et al. 1999), dynamic threshold voltage instability (Lu et al. 1997), and increased soft error rate (Wada et al. 1998). These have restricted the application of floating SOI, especially to analog circuits. Some circuit modifications and body contact insertions are necessary. A full body-fixing structure is another approach and some techniques have been proposed (Koh et al. 1997; Iwamatsu et al. 1995). However, when using these techniques, there have been some shortcomings in terms of scalability and layout compatibility. In this report, we propose a partial trench isolation (PTI) technique in which the body potential is fixed through the region under the trench oxide. With the PTI technology, we can eliminate floating-body effects while maintaining SOI-inherent merits and can realize scalable deep sub-quarter micron LSIs using accumulated bulk-design properties without layout modification. Moreover, the feasibility for ULSIs is demonstrated by a fully functional 4 Mbit SRAM.

70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications

We achieved 135 GHz f/sub max/ and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of V/sub th/ variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.

The Impact of Nitrogen Implantation into Highly Doped Polysilicon Gates for Highly Reliable and High-Performance Sub-Quarter-Micron Dual-Gate Complementary Metal Oxide Semiconductor

We studied the effects of nitrogen implantation into highly doped polysilicon gates in detail. It was found that highly arsenic-doped polysilicon gates caused degradation of gate oxide films and highly boron-doped polysilicon gates resulted in a shift of threshold voltage by boron penetration. Nitrogen implantation into polysilicon gates can effectively overcome these problems. The nitrogen implanted into the polysilicon gate is segregated into the gate oxide film during heat treatment after implantation. The nitrogen in the gate oxide film can act as a barrier layer for boron penetration and reduce the random failures of gate oxide films under highly doped polysilicon gates. Moreover, the hot carrier resistance can also be improved by nitrogen implantation. Highly reliable and high-performance dual-gate Complementary metal oxide semiconductor (CMOS) can be realized by the highly doped gate and the nitrogen implantation technique.

Feasibility of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

A 0.18 /spl mu/m silicon on insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology using hybrid trench isolation with high resistivity substrate is proposed and its feasibility for embedded RF/analog applications is demonstrated. The hybrid trench isolation is a combination of partial trench isolation and full trench isolation. In the partial trench isolation region, a part of the SOI layer remains under the field oxide so as to provide scalable body-tied SOI metal-oxide-semiconductor field-effect transistors (MOSFETs), while in the full trench isolation region, the whole of the SOI layer is replaced by the field oxide so as to provide high quality passives. It is demonstrated that this technology improves the maximum oscillation frequency and the minimum noise figure of the MOSFET and the Q-factor of the inductor, compared with bulk technology. Moreover, it is verified that the partial-trench-isolated body-tied structure suppresses the floating body effect of SOI devices for RF/analog applications and thus guarantees low-noise characteristics, stability, linearity, and reliability. It is concluded that this technology will be one of the key technologies for supporting the evolution of wireless communications.