Makoto Yabuuchi

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mum2 SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided VDD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245mum2 and 0.327mum2 are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition.

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.

A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits

We propose a new design scheme to improve the SRAM read and write operation margins in the presence of a large Vth variability. By applying this scheme to a 0.494 mum2 SRAM cell with a beta ratio of 1, which is an aggressively small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth value using a 65 nm LSTP CMOS technology

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

We propose a new 2-port SRAM with a single read bit line (SRBL) eight transistors (8 T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (Vt) random variations. A divided read bit line scheme with shared local amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous read and write (R/W) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A read end detecting replica circuit (RER) and a local read bit line dummy capacitance (LDC) are introduced to solve this issue. A 128 bit lines - 512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 mum2. This 2-port SRAM macro achieves 7 times faster access time without misreading.

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

We propose an access scheme for a synchronous dual- port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bit- line access scheme eliminates access conflict issues. Using 65 nm CMOS technology (hp90) with the proposed scheme, we fabricated 32 kB DP-SRAM macros. We obtained a 0.71 mum2 8T-DP-cell for which the cell size is only 1.44 times larger than a 6T-single-port (SP)- cell. The bit-density of the fabricated 32 kB DP-RAM macro is 667 kbit/mm2, which is 25% larger than a conventional 8T SRAM. The standby leakage is 27% less because of the small drive-NMOS transistor of the proposed 8T-DP-cell.

13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists

Scaling of process technology is inevitably accompanied by the increase of local variation in transistor characteristics, which has been deteriorating the operation margin of SRAM. This trend necessitates assist circuits for SRAM to increase the immunity against variations, and many papers in this area [1-4] have been published. In this paper, we present an assist circuit suitable for the SRAMs in 20nm generation. Figure 13.3.1 compares local variations of SRAM cell transistors, pass-gate NMOS (PG), pull-down NMOS (PD) and pull-up PMOS (PU) for 28 and 20nm, showing degradation as the process advances. Noticeably, the NMOS transistors become worse than PMOS, which causes degradation in SRAM operating margin since SRAM characteristics such as static noise margin (SNM) are more sensitive to NMOS than PMOS. Figure 13.3.1 also shows the operational window enclosed by read and write immunity against local variations in 28 and 20nm. This indicates assist circuits must perform beyond the level established in previously published work to address SRAM variation in advanced technology nodes. Lowering wordline (WL) voltage level is one of the read-assist approaches. Lowering the supply voltage of PU in a cell (ARVDD) and negative bitline (BL) techniques are known to be effective for the write operation. These techniques, however, have side-effects: lowering the WL voltage degrades write margin and lowering ARVDD leads to higher power consumption and a long cycle-time. Furthermore, the negative BL technique can cause write errors in non-selected columns. Thus, it is necessary to select which assist technique should be applied depending on each process technology. In addition, the SRAM used in production generally include single-port SRAM (SP-SRAM) and dual-port SRAM (DP-SRAM), so the assist circuits to be applied should be effective for whole SRAM family.

A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias

Voltage and technology scaling and increasing random variation in MOSFET characteristics reduce the operational margin of SRAM functionality, and several design techniques have been suggested to improve margins [1–3]. However, it is still difficult to achieve low-voltage operation (less than 1V) by design alone for devices such as sensor network applications using solar batteries. Design solutions combined with device techniques are required for robust SRAM operation and at the same time maintain low standby leakage.

A 65 nm Ultra-High-Density Dual-Port SRAM with 0.71um/sup ~/ 8T-Cell for SoC

We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71mum2 8T-DP-cell, which cell size is 1.44times larger than 6T-single-port (SP) cell