Motoyuki Sato

Practical Work Function Tuning Based on Physical and Chemical Nature of Interfacial Impurity in Ni-FUSI/SiON and HfSiON Systems

The paper demonstrates large effective work function (Phieff) modulation towards Si band-edges based on physical and chemical nature of interfacial impurities at Ni-FUSI/SiON and HfSiON interfaces. The authors clarify the influence of Ni-silicide phase on the Phieff modulation with dopant segregation. Phieff of 4.14 eV is obtained with a combination of phosphorous ion implantation last (IIL) doping and newly developed low temperature NiSi2 formation process. The paper also proposed the realistic Phieff modulation with Al-segregation at Ni-FUSI/HfSiON using IIL-doping process

Theoretical approach and precise description of PBTI in high-k gate dielectrics based on electron trap in pre-existing and stress-induced defects

We have theoretically analyzed the mechanism of PBTI degradation of high-k gate dielectrics. We proposed a PBTI degradation model based on a comprehensive physical theory using the general notation of gate leakage current and adequate trap distribution. Furthermore, by taking account not only pre-existing but also stress-induced defects, our model could explain the experimental data with high accuracy even though it was very simple. In addition, we have clarified that defect generation rate and/or capture cross-section in HfSiON is different from that in HfLaSiON.

Novel TDDB mechanism for p-FET accelerated by hydrogen from HfSiON film

Time Dependent Dielectric Breakdown (TDDB) in p-FETs with HfSiON/SiO2 gate stacks under negative bias stress has been studied. It is shown that the shape parameter of Weibull distribution of Tbd, β, is very small value independent of gate electrode materials. This small β seems to arise from the interface layer (I.L.) breakdown. Further experimental result reveals the existence of additional interface layer degradation mechanisms due to hydrogen in HfSiON. The reduction of hydrogen amount in high-k dielectrics leads to the longer-term reliability in metal-gate /high-k gate stacks.

Impact of Polarity of Gate Bias and Hf Concentration on Breakdown of HfSiON/

We have investigated the impact of polarity of gate bias and Hf concentration on HfSiON/SiO2 gate dielectric breakdown (DB) with time-zero DB (TZDB) and time-dependent DB (TDDB). At TZDB, the gate leakage currents at breakdown (BD) under negative bias are much smaller than those with positive bias without regard to accumulation or inversion states. Since the electric fields at BD are not all the same, the BD mechanism cannot be explained with a simple thermochemical model for all types of stress for HfSiON gate dielectric. With TDDB, the electric-field acceleration constant is dependent on the Hf concentration. Calculated active dipole moments in HfSiON have been shown to be similar to theoretical values for nMOS but not pMOS. Thermochemic BD of HfSiON, itself (not interface SiO2), is adequate to describe nMOS in the inversion state. On the other hand, the BD of pMOS in the inversion state is affected by the carrier currents and not the electric fields as the TZDB. The BD mechanisms are strongly dependent on both the polarity of the gate bias and the Hf concentration.

\hbox{SiO}_{2}

Sulfuric acid (H/sub 2/SO/sub 4/) and ozone (O/sub 3/) mixture process (SOM) with in-situ concentration monitor for O/sub 3/ and peroxyso-di-sulfuric acid (H/sub 2/S/sub 2/O/sub 8/) was developed Ultraviolet spectrometers with 190-200 nm and 254 nm of wavelength were used to detect H/sub 2/S/sub 2/O/sub 8/ and O/sub 3/ dissolved in SOM, respectively. In order to mix H/sub 2/SO/sub 4/ and O/sub 3/ effectively, the O/sub 3/ gas ejectors were jointed to a quartz bath directly. Using SOM process with UV oxidant monitors and O/sub 3/ gas ejectors, heavily dosed resist and dry etched resist could be removed perfectly without dry ashing process.

Gate Dielectrics

The authors have demonstrated the stacked MOCVD HfSiON gate dielectrics with extremely low Hf concentration (Hf/(Hf+Si)=6%) cap (LHC) which realized improved mobility and superior long-term reliability of CMOSFETs while maintaining low gate leakage currents and EOT scalability to 1nm. These superior electrical characteristics of the film are mainly owing to the suppression of the Vo2+ formation in the LHC layer, which is evidenced by first principle calculation

Photoresist stripping using novel sulfuric/ozone process

Vth control technology of HfSiON gate dielectrics by channel engineering using counter ion implantation method and fluorine or nitrogen ion implantation method are described. Current Ni-FUSI gate technology is also mentioned. Moreover, the authors explain breakdown mechanism of poly-Si/HfSiON/SiO2 gate stacks

Impact of Very Low Hf Concentration (Hf=6%) Cap Layer on Performance and Reliability Improvement of HfSiON -CMOSFET with EOT Scalable to 1nm

Microscopical investigation of leakage behaviors of Hf-based high-k gate stacks was achieved by means of electron-beam-induced current (EBIC) method. With this method, we could observe the pre-existing and stress induced defect in high-k. This pre-existing defect affect on MOSFET characteristics. We investigated in detail the relationship between the defect (in bulk high-k and interface) and 1/f noise on (110) and (100) substrates. The 1/f noise is strongly related to the degradation in the hole mobility due to the pre-existing defect or process integration damage. On the other hand, the 1/f noise of nMOSFETs is rerated to interface defects rather than electron mobility degradation.

HfSiON gate dielectric technology for CMOSFET application

Abstract We have clarified the impact of the activation annealing temperature on the NBTI and TDDB lifetime improvement of HfSiON / TiN gate stack pMOSFETs. Higher temperature annealing is effective for the NBTI and TDDB lifetime improvement. This is due to the Si substrate oxidation during the high temperature anneal resulting in the interface defect state reduction. And it is also effective for Vth reduction following device performance improvement.

Pre-existing and process induced defects in high-k gate dielectrics ∼direct observation with EBIC and impact on 1/f noise∼

A threshold voltage lowering of up to 400 mV in HfSiON/polycrystalline silicon (poly-Si) gate stack p-type metal–oxide–semiconductor field effect transistors (pMOSFETs) by fluorine incorporation into the channel is observed. Physical analysis verifies that implanted fluorine exists only in the channel region. The characteristics of the short-channel devices are investigated in detail, and an acceptor generation model by fluorine implantation is proposed. The model successfully explains the characteristics of fluorine-incorporated short-channel pMOSFETs.