Yoshitaka Tsunashima

Empty-space-in-silicon technique for fabricating a silicon-on-nothing structure

A promising technique to form the silicon-on-nothing structure is presented as an alternative to the silicon-on-insulator structure. A large plate-shaped empty space in silicon (ESS) below the surface of the silicon substrate can be fabricated by connecting the spherical empty spaces, which are formed by surface migration of Si on the patterned Si substrate. The ESS technique has the potential to change the microprocess for the fabrication of large-scale integrated circuits and it can be applied to various manufacturing technologies.

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

The process integration schemes for CMOS FinFET fabricated on bulk Si substrate are discussed from the viewpoints of device size scalability and short channel effect control. The trimming technique by special oxidation was applied to reduce fin width down to sub-10 nm regime. A novel punch through stopper (PTS) formation process was introduced to the bottom of the channel region to scale the gate length down to 20 nm. The combination of both process technology enables us to fabricate the smallest FinFET on bulk Si substrate reported to date

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with Lg = 15 nm and Wfin =15 nm at Vd= 1.0 V and Ioff= 100 nA/mum. Furthermore, the propagation delay time has been successfully improved down to less than 5 ps in the ring oscillator with DS-Schottky S/D CMOS-FinFET with 15 nm gate length

Improvement of threshold voltage deviation in damascene metal gate transistors

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, /spl Delta/V/sub th/ of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta/sub 2/O/sub 5/ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN.

Fabrication of Silicon-on-Nothing Structure by Substrate Engineering Using the Empty-Space-in-Silicon Formation Technique

A practical method for the fabrication of a silicon on nothing (SON) structure with the desired size and shape has been developed by using the empty-space-in-silicon (ESS) formation technique. It was found that the SON structure could be precisely controlled by the initial shape and layout of the trenches. The size of ESS is determined by the size of the initial trench. The desired shapes of ESS, such as spherical, pipe-shaped and plate-shaped, can be fabricated by changing the arrangement of the initial trenches. The fabricated SON region over ESS has excellent crystallinity adoptable for ultra-large-scale integrated circuit (ULSI) applications. The SON structure would be a promising substrate structure for various manufacturing technologies, such as the micro-electro-mechanical system (MEMS), photonic crystals and waveguides.

Micro-structure Transformation of Silicon: A Newly Developed Transformation Technology for Patterning Silicon Surfaces using the Surface Migration of Silicon Atoms by Hydrogen Annealing

The micro-structure transformation of silicon (MSTS), which is a transformation technology for patterning silicon surfaces by hydrogen annealing, is presented for the first time. The transformation was controlled by the parameters of annealing pressure as well as annealing time and temperature. Voids of sub-micrometer regime size can be intentionally formed in the silicon substrates by making use of transformation. Electrical characteristics, such as the reliability of the thin dielectrics formed in the deep trenches, were improved with the aid of the MSTS process, due to the flattening of the inside surface of the trenches and the rounding of the corners. The mechanism of the transformation by MSTS was studied by means of molecular dynamics, which clearly shows the migration of silicon atoms on the surface. MSTS is a promising technology for the fabrication of future integrated circuits in silicon.

Nitrogen profile control by plasma nitridation technique for poly-Si gate HfSiON CMOSFET with excellent interface property and ultra-low leakage current

A comparative study of plasma and thermal nitridation of HfSiO was performed systematically. We found that over 15 atom% of nitrogen is necessary to obtain sufficient thermal stability and blocking of boron diffusion in a conventional polycrystalline Si gate CMOS process regardless of the nitridation method. However, we demonstrated, for the first time, that plasma nitridation has a great advantage for obtaining thinner equivalent oxide thickness, lower gate leakage current (J/sub g//J/sub g/SiO/sub 2/=1E-4 @ V/sub g/=V/sub fb/-1 V) and higher carrier mobility (/spl mu//sub eff///spl mu//sub eff/SiO/sub 2/=0.85 @ E/sub eff/=0.8 MV/cm for electron, /spl mu//sub eff///spl mu//sub eff/SiO/sub 2/=0.9 @ E/sub eff/=0.5 MV/cm for hole) due to nitridation of HfSiO film without nitridation of Si substrate, compared with thermal nitridation.

Novel corner rounding process for shallow trench isolation utilizing MSTS (Micro-Structure Transformation of Silicon)

A new STI (Shallow Trench Isolation) corner rounding technique with MSTS (Micro-Structure Transformation of Silicon) which utilizes Si-migration phenomenon with hydrogen ambient annealing is proposed and applied to 0.15 /spl mu/m CMOS technology. Highly controlled corner rounding radius is achieved without high temperature oxidation process. Thus it is free from defect generation and undesirable impurity diffusion in the Si substrate. Subthreshold current due to parasitic corner transistors of the STI structure is effectively suppressed and the reverse narrow channel effect is controlled down to 0.2 /spl mu/m channel width.

A new substrate engineering for the formation of empty space in silicon (ESS) induced by silicon surface migration

A new technique to form empty spaces in silicon substrates is presented. The empty space with various shapes, such as plate as well as sphere and pipe, could be formed under the surface of the silicon substrate.

Trench transformation technology using hydrogen annealing for realizing highly reliable device structure with thin dielectric films

The shape and the surface morphology of the trench structure was successfully transformed by the annealing in hydrogen ambient. The corner was rounded and the surface morphology was smoothened on the inside of the trench. Electrical characteristics of the thin oxide grown in the deep trench capacitor were drastically improved. The hydrogen annealing condition was optimized based on the transformation mechanism.