Seiji Inumiya

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

Effects of nitrogen in HfSiON gate dielectric on the electrical and thermal characteristics

The effects of the nitrogen in the HfSiON gate dielectric on the electrical and thermal properties of the dielectric were investigated. It is clearly demonstrated that nitrogen enhances the dielectric constant of silicates. High dielectric constants of the HfSiON are maintained and boron penetration is substantially suppressed in the HfSiON during high temperature annealing. These properties are ascribed to the homogeneity of the bond structure in the film containing nitrogen through high temperature annealing.

Improvement of threshold voltage deviation in damascene metal gate transistors

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, /spl Delta/V/sub th/ of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta/sub 2/O/sub 5/ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN.

Nitrogen profile control by plasma nitridation technique for poly-Si gate HfSiON CMOSFET with excellent interface property and ultra-low leakage current

A comparative study of plasma and thermal nitridation of HfSiO was performed systematically. We found that over 15 atom% of nitrogen is necessary to obtain sufficient thermal stability and blocking of boron diffusion in a conventional polycrystalline Si gate CMOS process regardless of the nitridation method. However, we demonstrated, for the first time, that plasma nitridation has a great advantage for obtaining thinner equivalent oxide thickness, lower gate leakage current (J/sub g//J/sub g/SiO/sub 2/=1E-4 @ V/sub g/=V/sub fb/-1 V) and higher carrier mobility (/spl mu//sub eff///spl mu//sub eff/SiO/sub 2/=0.85 @ E/sub eff/=0.8 MV/cm for electron, /spl mu//sub eff///spl mu//sub eff/SiO/sub 2/=0.9 @ E/sub eff/=0.5 MV/cm for hole) due to nitridation of HfSiO film without nitridation of Si substrate, compared with thermal nitridation.

High performance damascene metal gate MOSFETs for 0.1 /spl mu/m regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (/spl sim/1000/spl deg/C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450/spl deg/C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO/sub 2/ or Ta/sub 2/O/sub 5/ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance.

Careful examination on the asymmetric Vfb shift problem for poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the poly-Si interface with small EOT expense

In this paper, the effect of the MIGS and the poly-Si process on the Vfb shift was carefully examined and clarified. We conclude that these factors are not correlated with the shift. We found that lowering the Htf (Hf+Si) (Hf-ratio) in HfSiON below 10% leads to the significant suppression of this shift in both NMOS and PMOS. We also demonstrated that the insertion of ultra-thin cap layers into the poly-Si/HfSiON results in Vfb improvement with 0.1 nm EOT expense. We proposed that the sophisticated tailoring of Hf in the dielectric could be a practical solution for the Vfb improvement.

Fabrication of HfSiON gate dielectrics by plasma oxidation and nitridation, optimized for 65 nm mode low power CMOS applications

Fabrication process of HfSiON gate dielectrics by plasma oxidation of CVD Hf silicate followed by plasma nitridation was developed. Thanks to the high quality ultrathin interfacial layer formed by internal plasma oxidation, electron mobility of 240 cm/sup 2//Vs@0.8 MV/cm (85% of SiO/sub 2/) and hole mobility of 73 cm/sup 2//Vs@0.5 MV/cm (93% of SiON) were successfully achieved. The developed process will be promising for the production of low power CMOS devices in the near future.

Characterization of HfSiON gate dielectrics using monoenergetic positron beams

The impact of nitridation on open volumes in thin HfSiOx films fabricated on Si substrates by atomic layer deposition was studied using monoenergetic positron beams. For HfSiOx, positrons were found to annihilate from the trapped state due to open volumes which exist intrinsically in an amorphous structure. After plasma nitridation, the size of open volumes decreased at a nitrogen concentration of about 20at.%. An expansion of open volumes, however, was observed after postnitridation annealing (PNA) (1050°C, 5s). We found that the size of open volumes increased with increasing nitrogen concentration in HfSiOx. The change in the size of open volumes was attributed to the trapping of nitrogen by open volumes, and an incorporation of nitrogen into the amorphous matrix of HfSiOx during PNA. We also examined the role of nitrogen in HfSiOx using x-ray photoelectron spectroscopy and first principles calculations.

Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) with low threshold voltage, high drive current, and uniform electrical characteristics

We propose dynamic threshold-voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation (0.7 V). By using this technology, we found that low threshold voltage (about 0.15 V reduction for CMOS), high drive current, excellent subthreshold swing (about 60 mV/decade), and uniform electrical characteristics (great reduction of threshold voltage deviation) were obtained in the transistors with mid-gap work function metal gates (Al/TiN or W/TiN) and low supply voltage (0.7 V).

Conformable formation of high quality ultra-thin amorphous Ta/sub 2/O/sub 5/ gate dielectrics utilizing water assisted deposition (WAD) for sub 50 nm damascene metal gate MOSFETs

A conformable formation process of ultra-thin Ta/sub 2/O/sub 5/ gate dielectrics, which is applicable to 50 nm damascene gate MOSFETs, was developed. Assisted by H/sub 2/O, perfect conformability was successfully realized even in the narrow gate groove (50 nm), while maintaining a low gate leakage. An excellent device performance of S-factor 72 mV/decade was obtained in 90 nm MOSFET with amorphous Ta/sub 2/O/sub 5/ gate dielectrics of T/sub eff/ 1.6 nm.