Claudia Rusu

Configurable serial fault-tolerant link for communication in 3D integrated systems

Three-dimensional (3D) Thru-Silicon-Via (TSV) integration is emerging as a key enabling technology for future high performance systems. The TSV manufacturing defect rates lead to significant interconnect yield loss. For intra-die and inter-die interconnects, techniques such as via widening, via spreading and spare via insertion have been successfully used to improve the yield. However, for high fault rates these solutions are less effective and lead to unacceptable overheads. In this paper, configurable serial fault tolerant links are proposed for inter-die communication in 3D integrated systems. For high TSV fault rates, serial data transmission and signal remapping on fault-free wires are jointly used to ensure correct data transmission. After the interconnect tests, if faulty wires are detected then the link serializes data transmission such that only fault free wires are used. In the proposed link, any subset of data bits can be mapped on any subset of functional wires. Selecting a threshold serialization rate above which the link fails, enables optimal link designs that target interconnect technologies with high fault rates. The impact of inter-die configurable serial fault tolerant links on the performance and area overheads of 3D mesh networks-on-chip (3D NoC) is analyzed. The results show that for an 80% interconnect fault rate the latency degradation up to 14% and area overheads go up to 30%.

A flexible network-on-chip simulator for early design space exploration

The communication requirements of large multi-core systems are convened by on-chip communication fabrics generally referred to as networks-on-chip (NoC). We have designed a simulation environment that allows early exploration of the performance and cost parameters of network-on-chip communication architectures, which is able to handle arbitrary topologies and routing schemes. The simulator implements a flit-level message-passing mechanism and supports application data specified as input trace files or generated at run-time by synthetic traffic generators.

Message routing in 3D networks-on-chip

Nowadays 3D chips are fabricated by stacking 2D layers and manufacturing vertical links between them. In this paper we present a routing scheme suited for 3D networks-on-chip (NoCs). It is based on the reuse of existing routing schemes for 2D NoCs. Our 3D scheme is scalable and can be used with any 2D topology. The effectiveness of the scheme for intra-layer communication is given by the respective 2D routing scheme of each layer, while for the inter-layer communication the scheme can always find a route between any source and destination, if there is one available.

Adaptive inter-layer message routing in 3D networks-on-chip

Existing routing algorithms for 3D deal with regular mesh/torus 3D topologies. Today 3D NoCs are quite irregular, especially those with heterogeneous layers. In this paper, we present a routing algorithm targeting 3D networks-on-chip (NoCs) with incomplete sets of vertical links between adjacent layers. The routing algorithm tolerates multiple link and node failures, in the case of absence of NoC partitioning. In addition, it deals with congestion. The routing algorithm for 3D NoCs preserves the deadlock-free propriety of the chosen 2D routing algorithms. It is also scalable and supports a local reconfiguration that complements the reconfiguration of the 2D routing algorithms in case of failures of nodes or links. The algorithm incurs a small overhead in terms of exchanged messages for reconfiguration and does not introduce significant additional complexity in the routers. Theoretical analysis of the 3D routing algorithm is provided and validated by simulations for different traffic loads and failure rates.

RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip

In the context of the emerging 3D integration paradigm, chips are built as stacks of several (likely heterogeneous) 2D layers. The topology of their communication network is quite irregular, mainly due to the different topologies of the 2D layers and the partial vertical connection between these layers. In this paper, a reconfigurable inter-layer routing mechanism (RILM) for such topologies is proposed. We firstly present the mechanism of composing the routing algorithms in different layers, through the vertical links, in order to achieve a multi-layer routing algorithm. Reconfiguration of the routing can be done for multiple reasons: to achieve fault-tolerant capability, but also under dynamic changing of the communication requirements, or, simply, to avoid congestions. To obtain a complete routing reconfiguration for the entire stack of layers, we propose a reconfiguration algorithm of the inter-layer routes, as a complement to the 2D routing reconfiguration. Additionally, independently of the 2D routing algorithm properties, RILM tolerates multiple failures of vertical links, as long as the stack of layers is not partitioned.

Improving the scalability of checkpoint recovery for networks-on-chip

This paper proposes a method of improving the scalability of checkpoint recovery for network-on-chip based systems in terms of checkpointing latency and memory requirements. The improvement considers the broadcasts implied in the checkpointing protocol. It combines the reduction of the number of broadcasts in the checkpoint synchronization protocol with the use of a more efficient broadcast method at network level.

Error resilience of intra-die and inter-die communication with 3D Spidergon STNoC

Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high performance integrated circuits wires become the performance bottleneck and we are shifting towards communication centric design paradigms. Networks-on-chip and stacked 3D integration are two emerging technologies that alleviate the performance difficulties of on-chip interconnects in nano-scale designs. In this paper we present a design-time configurable error correction scheme integrated at link-level in the 3D Spidergon STNoC on-chip communication platform. The proposed scheme detects errors and selectively corrects them on the fly, depending on the critical nature of the transmitted information, making thus the correction software controllable. Moreover, the proposed scheme can correct multiple error patterns by using interleaved single error correction codes, providing an increased level of reliability. The performance of the link and its cost in silicon and vertical wires are evaluated for various configurations.

Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems

This paper presents and compares two failure recovery schemes developed for multi-core systems-on- chip that use network-on-chip communication infrastructures. The failure recovery methods are aimed towards fast recovery from system or application failures, when global reset is the last resort to recover a failed system. The first method uses coordinated checkpointing, while the second is based on uncoordinated checkpointing and message logging. Their effectiveness and overhead are evaluated and compared, under different application traffic loads and failure rates.

Communication Aware Recovery Configurations for Networks-on-Chip

In this paper we propose a set of different configurations of failure recovery schemes, developed for network-on-chip (NoC) based systems. These configurations exploit the fact that communication in NoCs tends to be partitioned and eventually localized. The failure recovery approach is based on checkpoint and rollback and is aimed towards fast recovery from system or application level failures. The proposed recovery configurations and partitions of the NoC enhance the performance/overhead of the recovery mechanism. We analyze the effectiveness of these solutions, depending on the traffic characteristics and the expected failure rate.

Configurable fault-tolerant link for inter-die communication in 3D on-chip networks

3D integration is a technological innovation that promises improved performance at lower dissipated power of integrated circuits by stacking silicon layers connected with special vertical wires called Thru-Silicon-Vias (TSVs) [1]. The increasing delay and high dissipated power of global interconnects in advanced 2D technologies is not alleviated by replacing these long wires (~mm) with shorter TSVs (~ tens of µm). In 3D systems-on-chip (SoCs), the functional (Intellectual Property IP) blocks are distributed across the layers of the stack. The interconnect fabric on which the systems IP blocks communicate must ensure high performance and flexibility of designs by implementing communication protocols at different abstraction layers. 3D networks-on-chip (NoCs) are among the proposed solutions for scalable high performance and low power communication. 3D NoCs consists in routing nodes attached to the IP blocks that have intra-die and inter-die links.