Vladimir Pasca

Configurable serial fault-tolerant link for communication in 3D integrated systems

Three-dimensional (3D) Thru-Silicon-Via (TSV) integration is emerging as a key enabling technology for future high performance systems. The TSV manufacturing defect rates lead to significant interconnect yield loss. For intra-die and inter-die interconnects, techniques such as via widening, via spreading and spare via insertion have been successfully used to improve the yield. However, for high fault rates these solutions are less effective and lead to unacceptable overheads. In this paper, configurable serial fault tolerant links are proposed for inter-die communication in 3D integrated systems. For high TSV fault rates, serial data transmission and signal remapping on fault-free wires are jointly used to ensure correct data transmission. After the interconnect tests, if faulty wires are detected then the link serializes data transmission such that only fault free wires are used. In the proposed link, any subset of data bits can be mapped on any subset of functional wires. Selecting a threshold serialization rate above which the link fails, enables optimal link designs that target interconnect technologies with high fault rates. The impact of inter-die configurable serial fault tolerant links on the performance and area overheads of 3D mesh networks-on-chip (3D NoC) is analyzed. The results show that for an 80% interconnect fault rate the latency degradation up to 14% and area overheads go up to 30%.

Through-silicon-via built-in self-repair for aggressive 3D integration

Three-dimensional (3D) integration by die-/wafer-level stacking becomes a reality, as Through-Silicon-Via technologies emerge. However, poor reliability and yield of TSV interconnects remain major challenges of this promising technology. In this paper, we propose an efficient Built-In Self-Repair (TSV-BISR) strategy for TSV faults due to manufacturing and aging defects. After interconnect tests, we replace faulty TSVs with fault-free spares using shift operations. Among the benefits of this solution is that the self-repair signals are determined on-chip without any external intervention. Moreover, we show that with TSV-BISR better reparability is achieved with fewer spares than in existing TSV repair techniques. We also show that for 3D chips with interconnect reparability targets above 98% we reduce the area needed for spares and repair logic by up to 40%.

Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis

Three-dimensional integration is a key technology for systems whose performance / power requirements cannot be achieved by traditional silicon technologies. Testing is one of the major challenges of 3D integration. This paper proposes a configurable Interconnect Built-In Self-Test (BIST) technique for inter-die interconnects (Thru-Silicon Vias TSVs). The proposed technique accounts for faults like opens and shorts and also delay faults due to crosstalk. In the proposed fault model, the signal transitions on victim TSVs are affected by the transitions on the aggressor TSVs. The Kth Aggressor Fault model (KAF) assumes that the aggressors of each victim TSV are the K-order neighbors. The test times are reduced as more victim TSVs are concurrently tested. The neighboring order K is technology dependent and it is determined such that the test times are minimal without loss in fault coverage. The proposed BIST has lower area than existing interconnect BIST solutions, while the configuration capabilities increase the area by up to 80%. However, due to relative high TSV pitch (10s μm), the area overheads are small.

Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis

Three-dimensional (3D) integration is a key technology for systems whose performance and power requirements cannot be achieved by traditional silicon technologies. 3D chips consist of two or more stacked silicon dies connected by short inter-die wires called Thru-Silicon-Vias (TSVs). Despite its potential, the poor reliability and yield, thermal management and testing issues remain major challenges of 3D integration. We address the TSV interconnect test challenge of 3D chips by using Interconnect Built-In Self-Test (IBIST) techniques. The proposed test strategy must sensitize structural faults like opens and shorts, and delay faults due to crosstalk. A possible approach is the well-known Maximum Aggressor Fault (MAF) model. Unfortunately, this model is too conservative and it leads to long test sequences and non-negligible hardware costs. Therefore, we present an alternative solution: the Kth-Aggressor Fault (KAF) model. In our model, aggressors of victim wires are neighboring wires within an optimized distance order K. The aggressor order K is technology-dependent and is determined such that the test times are minimal and the fault coverage is maximal. KAF-based IBIST implementation targeting TSV tests occupies three times less area than similar MAF-/marching-based implementations. We also propose a reconfigurable KAF-based IBIST implementation where tests can be performed using different aggressor orders K. Although the reconfigurable IBIST area is significant, interconnect tests during system lifetime can be performed using lower aggressor orders, reducing test duration and improving TSV availability.

CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems

Three dimensional (3D) integrated systems become a reality nowadays, as Thru-Silicon-Via (TSV) technologies mature. 3D integration promises significant performance and energy efficiency improvements by reducing the signal travel distances and integrating more capabilities on a single chip. High integration costs, thermal management, and poor reliability and yield are major challenges of TSV based 3D chips. High structural and parametric fault rates due to manufacturing defects makes it difficult to achieve high interconnect yield using only spare-based repair solutions. In this paper we address the TSV yield issue by implementing the inter-die links of 3D chips as Configurable fault-tolerant Serial Links (CSLs). When there are not enough available functional TSVs, faults are tolerated by performing data serialization. CSLs help reduce chip costs by improving the TSV yield with very few or no spares at all. For 3D Networks-on-Chip (3D NoCs) we show that the CSL yield improvement comes with moderate area overheads (~12–26%) and small performance penalties (less than 5% average latency overhead).

Error resilience of intra-die and inter-die communication with 3D Spidergon STNoC

Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high performance integrated circuits wires become the performance bottleneck and we are shifting towards communication centric design paradigms. Networks-on-chip and stacked 3D integration are two emerging technologies that alleviate the performance difficulties of on-chip interconnects in nano-scale designs. In this paper we present a design-time configurable error correction scheme integrated at link-level in the 3D Spidergon STNoC on-chip communication platform. The proposed scheme detects errors and selectively corrects them on the fly, depending on the critical nature of the transmitted information, making thus the correction software controllable. Moreover, the proposed scheme can correct multiple error patterns by using interleaved single error correction codes, providing an increased level of reliability. The performance of the link and its cost in silicon and vertical wires are evaluated for various configurations.

Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems

The high defect rates of the TSV manufacturing processes lead to poor yield [1]. Interconnect repair and serialization techniques were proposed [1–2] to improve yield. In these papers the control of the repair and serialization circuitry are determined off-chip and are stored in one-time-programmable memories. In this work we present an Interconnect Built-In Self-Repair and Adaptive-Serialization approach (I-BIRAS), where interconnect repair and data serialization/deserialization is performed without external intervention (reducing cost of external equipment) and can be executed at any time (after fabrication and all along system life), thus coping with both fabrication and systemlife defects. The general architecture of our approach is shown in figure 1.

Fault tolerant communication in 3D integrated systems

3D integration is an emerging technology that promises higher integration densities and performances and low power dissipation. Stacked 3D integrated systems consist in layers of active silicon connected with vertical wires called Thru-Silicon-Vias (TSV). The high defect rates of 3D systems cumulate the intra-die and inter-die interconnect parametric variations. Thus, the susceptibility to permanent and transient faults increases. In this paper fault tolerant communication in 3D systems is achieved by spare via insertion and signal coding. As single error correction (SEC) capabilities are not enough to ensure the targeted level of communication reliability in 3D technologies, multi-error correction capabilities are achieved by block/ interleaved SEC codes. Data bits are split in blocks, individually encoded using SEC codes. Due to current 3D integrated manufacturing processes, achieving a good yield is one of the current challenges of this technology. In this paper, interconnect yield improvement is achieved auto reconfiguration by using spare via insertion.

Efficient link-level error resilience in 3D NoCs

Due to their scalability and flexibility, Networks-on-Chip are among the most popular communication fabrics for 3D integrated systems. 3D NoCs consist of a mix of inter-die and intra-die links implemented in different technologies. Thus, in order to guarantee correct data transmission through the 3D NoC, link reliability must be ensured. Error resilience techniques have been developed to protect links at the expense of increased area and power consumption, and reduced performance. In this paper, error resilience schemes are implemented for NoC links in stacked 3D integrated systems. We analyze, with respect to area / power overheads and reliability, the impact of inter-die and intra-die link-level error resilience techniques on a 3D NoC router architecture. Our results show that inter-die link protection with correction-based schemes and interleaved single error correction (SEC) codes are more efficient than traditional protection on all links.

I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems

In 3D integrated systems, Thru-Silicon-Vias (TSVs) enable higher performance and energy efficiency, by reducing the data travel distances. However, the TSV manufacturing and wear-out defect rates lead to poor interconnect reliability and yield. The high fault rates and TSV footprint make spare-based repair solutions inefficient. I-BIRAS combines self-repair and adaptive serialization to increase yield and circuit life at the cost of lower throughput. After the interconnect test, the diagnosis vector DV is used to perform the self-repair and adaptive serialization to increase yield and circuit life at the cost of lower throughput. After the interconnect test, the diagnosis vector DV is used to perform the self-repair and adaptive serialization. The design parameters are the number of data bits n, the number of spare TSVs r, and the minimum acceptable number mLIMIT of fault-free TSVs. If the number of fault-free TSVs is less than mLIMIT then the link assumed failed.