Mousumi Saha

Synthesis of Reversible Universal Logic around QCA with Online Testability

Quantum-dot Cellular Automata (QCA) can be a viable technology for CMPs (chip multi-processors) with thousands of processors. The QCA based reversible logic promises energy efficient design of the digital circuits. However, the requirement of excessive logic gates as well as its high defect rate limit the performance of a QCA based design. This work proposes a new approach to synthesize the reversible universal QCA logic gate (RUG) with the target to reduce the garbage outputs as well as the number of logic gates to realise a design simultaneously ensuring the defect tolerance. A concurrent error detection methodology is introduced to support the online testing of a circuit designed around the RUG. The experimental designs establish that the RUG can ensure an energy saving cost effective realization of testable QCA circuits.

A cellular automata based design of self testable hardware for March C

The March tests are extensively used for functional test of SRAMs and DRAMs. This work reports hardware realization of March C to enable high speed detection of faults in memories. It is developed around a special class of cellular automata (CA) with the target to achieve a test structure self testable. The regular structure of CA enables low cost implementation of test logic for the memory chip that is inherently regular in structure. The CA memorizes the status (faulty/non-faulty) of memory words as well as its own defects during read (r0/r1) operation of the March algorithm. The final state of the n-cell CA, employed for the test hardware, indicates the faults (if any) in a memory word or in the test logic. It effectively reduces the overhead of bit by bit comparison of memory words, that is required in a conventional test structure, to take decision on the faults in memory.

A cellular automata based highly accurate memory test hardware realizing March C

This work reports a highly accurate test structure for high speed memories. The theoretical bases of the design are the March algorithm and cellular automata (CA) proposed by von Neumann in 1950s. Theory of 3 and 5-neighborhood CA, employed for the current application, has been developed to enhance the self-testability of memory test logic. The special class of single length cycle attractor cellular automata, introduced in this work, accepts status of each memory word and evaluates it to decide on the faults in the memory. The extension of CA neighborhood to 5 enables propagation of the effect of faults in memory or in the test logic to the error line of the test structure. This overcomes the inability of classical memory test hardware designed with the ex - or and or logic.

High Speed Hardware for March C

The variations of March tests are extensively used for functional test of SRAMs and DRAMs. This work proposes hardware realization of March C- to enable efficient fault detection in memories. The properties of single length cycle attractor cellular automata are exploited to memorize the status (faulty/non-faulty) of memory words during read (r0/r1) operation of the March C- algorithm. It effectively reduces the overhead of comparison that is required in a conventional test structure, to take decision on the faults in memory.

Cellular automata based fault tolerant resistive memory design

This work reports a fault tolerant design for the high density resistive memories. It addresses the limitation of low cell reliability of resistive memories and the restricted write endurance. The faulty and worn-out cells of a memory module are identified on-line to recover from the damage caused during the life time of a chip. Von Neumanns theory of cellular automata has been used as a basis of the reported design. The single length cycle cellular automata (SACA) is synthesized to capture the erronous recording in a memory cell during a write and memorizes the stuck-at value stored there of. It enables effective retrieval of data during a read, that is desired for the high density resistive memories.

Design of an Efficient Scheme for Data Migration in Chip-Multiprocessors

Chip Multiprocessors (CMPs) with non-uniform cache architecture (NUCA) realizes thousands of processor cores on-chip. This work proposes an efficient scheme for data migration in CMPs, during program execution, for exploiting benefits of such design with NUCA. The scheme is developed around the modelling tool of periodic boundary cellular automata (CA). The CA employed performs density classification of the instances of data request generated by different cores. The outcome of the CA run (classification)indicates direction of data movement towards the region populated with processors requesting for the data block. It effectively reduces the time taken for the decision on data migration as well as ensures most accurate decision.

Poster: Exploring Visible Light Communication System using RTS/CTS Mechanism for Mobile Environment

This work presents a software-centric visible light communication (VLC) system in full duplex mode with CSMA/CA and RTS-CTS in mobile environment. We focus on channel access mechanism problems in the same environment. To solve these we modify Distributed Coordination function (DCF) by adding ambient light measurement slot. The result shows modified DCF can handle the problems.

Periodic boundary cellular automata based test structure for memory

This work reports an effective test design for memory. It realizes March algorithm employing a periodic boundary cellular automata (PBCA) structure. The irreversible single length cycle attractor cellular automata (CA), selected for the design, returns correct decision on the fault in memory even if the test logic is defective. It avoids the bit by bit comparison of memory words, practiced in the conventional test designs, and outperforms the state-of-the-art memory test architecture in terms of delay in testing. The hardware overhead of CA based test design is insignificant in comparison to the cost of memory.

Multi-bit fault tolerant design for resistive memories through dynamic partitioning

This work proposes a fault diagnosis methodology intended for resistive memories. Multiple cells of a block may suffer from stuck-at faults during repetitive write operations in resistive memory. It causes serious hindrance to large scale adoption of resistive memory. This issue is addressed through introduction of von Neumanns Cellular Automata (CA). The two single length cycle attractor CA (TACA) and single single length cycle attractor CA (SACA) are synthesized to capture the erroneous bit positions of memory blocks in run time. It ensures the correct retrieval of data and fulfills the requirement of an efficient fault tolerant resistive memory subsystem.

On detecting acceptable air contamination in classrooms using low cost sensors

In present scenario of the world, environmental pollution is one of the leading challenges. Most often the educational institutes and organizations in developing countries suffer from polluted environment due to overcrowded rooms, improper planning and poor infrastructure. Students/faculties in a classroom could suffer from health issues due to prolonged exposure to such environment. On an average a student/faculty is exposed to such environment for eight hours per day. A student/faculty could undergo physical as well as cognitive hazards. This paper tends to detect the duration for which a classroom environment can be considered healthy for a given number of students. We built an Air Quality Monitoring Unit using low cost gas sensors which could compare the air contamination level of the environment with specified standards to detect when the environment tends to get uncomfortable for students/faculties. This in turn could result in reduced absentees and improved performance of students/faculties. Some useful results came to our observation such as, in a class of 30 students the concentration level of CO2 increases about 28.14% as compared to empty classroom whereas in a class of 40 students in the same classroom it increases about 55.33% in a duration of 2 hours.