Baisakhi Das

Design of an Efficient Scheme for Data Migration in Chip-Multiprocessors

Chip Multiprocessors (CMPs) with non-uniform cache architecture (NUCA) realizes thousands of processor cores on-chip. This work proposes an efficient scheme for data migration in CMPs, during program execution, for exploiting benefits of such design with NUCA. The scheme is developed around the modelling tool of periodic boundary cellular automata (CA). The CA employed performs density classification of the instances of data request generated by different cores. The outcome of the CA run (classification)indicates direction of data movement towards the region populated with processors requesting for the data block. It effectively reduces the time taken for the decision on data migration as well as ensures most accurate decision.

Exploring Impact of Faults on Branch Predictors' Power for Diagnosis of Faulty Module

Out of the several factors responsible for processor power dissipation, the branch prediction unit itself contributes to almost 10% of the overall processor power dissipation. The functioning of predictors is, therefore, to be more accurate especially for the CMPs (chip multiprocessors) with thousands of on-chip cores. This work reports that the design inaccuracy (fault) in a predictor can cause a huge power loss, even up to95%. The impact of faults causing additional loss in processor power is estimated to diagnose the faulty module of a predictor. This has been established through introduction of probable faults/design inaccuracies to each of the functional modules of a predictor. Exhaustive experimentations on the state-of-the-art predictors reveal that the amount of additional power loss during processor execution clearly points to the specific design inaccuracies. This effectively leads to identification of the faulty module of a predictor.

Evaluation of Misspeculation Impact on Chip-Multiprocessors Power Overhead

The main reason for low efficiency of data cache in chip-multiprocessors (CMPs) is the presence of dead blocks that are not accessed for a long time before eviction. The design inaccuracies degrade the performance of a system and cause huge power drainage. This demands effective prediction scheme for the early detection of dead block. This work, therefore, targets to study the impact of faults/inaccuracies in prediction (misspeculation) causing additional loss in processor power. Further, the power loss for misspeculation in data migration is evaluated. The analysis of experimental results reveals that the misspeculation needs to be avoided in CMPs to ensure effectiveness of such a system.

Periodic boundary cellular automata based test structure for memory

This work reports an effective test design for memory. It realizes March algorithm employing a periodic boundary cellular automata (PBCA) structure. The irreversible single length cycle attractor cellular automata (CA), selected for the design, returns correct decision on the fault in memory even if the test logic is defective. It avoids the bit by bit comparison of memory words, practiced in the conventional test designs, and outperforms the state-of-the-art memory test architecture in terms of delay in testing. The hardware overhead of CA based test design is insignificant in comparison to the cost of memory.

Design of CA based scheme for evenhanded data migration in CMPs

This work reports realization of close to accurate data migration in Chip Multiprocessors (CMPs). The periodic boundary cellular automata (PBCA) is introduced to accept the requests from processor cores competing for a data block and to perform accurate density classification of the requesting processors. The CA enables identification of populated region of requesting cores and thereby points to the area of migration. The design is enriched to favor the processor cores in isolation and to decide on the area of migration to avoid performance loss of such processors.

A CA based scheme of cache zone prediction for data migration In CMPs

This work proposes an efficient scheme for identification of L2 cache module zone (low level cache) for data migration in Chip Multiprocessors (CMPs), during program execution, exploiting the benefits of Non-Uniform Cache Architecture (NUCA). Selection of an exact cache module for migration is always not realizable. A more efficient scheme can be the prediction of cache zone for migration. The proposed scheme is developed around the modelling tool of periodic boundary cellular automata (CA) to satisfy the requirement. The CA employed performs density classification of the instances of data request generated by different processor cores and predicts the best placement for data (up to an acceptable level) in the low level NUCA cache.

An efficient scheme for data block migration in tiled CMPs cache system

This work proposes efficient data (cache block) migration in Chip Multiprocessors (CMPs) realizing nonuniform cache architecture (NUCA). The scheme is developed around the modeling tool of cellular automata (CA) invented by von Neumann in 1950s. A special class of periodic boundary CA (PBCA) has been introduced to analyze the distribution of processor cores competing for a data block. It performs density classification of the instances of requests generated by different cores and then decides on the migration of requested block among the L2 cache banks. The PBCA correctly identifies the region populated with processors competing for the data block and points to the direction of data migration. It effectively realizes the quick decision on data migration as well as ensures the most accurate decision.