Mrinal Goswami

Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability

The quantum-dot cellular automata have emerged as one of the potential computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. On the other hand, reversible computing promises low power consuming circuits by nullifying the energy dissipation during the computation. This work targets the design of a reversible arithmetic logic unit (RALU) in the quantum-dot cellular automata (QCA) framework. The design is based on the reversible multiplexer (RM) synthesized by compact 2:1 QCA multiplexers introduced in this paper. The proposed reversible multiplexer is able to achieve 100% fault tolerance in the presence of single missing or additional cell defects in QCA layout. Furthermore, the advantage of modular design of reversible multiplexer is shown by its application in synthesizing the RALU with separate reversible arithmetic unit (RAU) and reversible logic unit (RLU). The RALU circuit can be tested for classical unidirectional stuck-at faults using the constant variable used in this design. The experimentation establishes that the proposed RALU outperforms the conventional reversible ALU in terms of programming flexibility and testability. HighlightsA reversible QCA multiplexer logic (RM) is designed from irreversible multiplexer.Results show the effectiveness of the design in terms of cost and testing overhead.Fault testing capability is reported.A complete testable reversible arithmetic logic unit (RALU) is synthesized based on separate module of RAU and RLU.Reliability issue is addressed with modularity.

Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers

Display Omitted A modular design methodology around multiplexer is designed.This work make a trade-off between modular design and its reliability associated with fault tolerance and energy consumptions.Cascading lower order multiplexer to synthesize higher order multiplexer mitigating wire crossing and delay.Application of proposed design in CLB is also done. With the rapid advancement in very large scale integration (VLSI) technology, it is the utmost necessity to achieve a reliable design with low power consumption. The Quantum dot Cellular Automata (QCA) can be such an architecture at nano-scale and thus emerges as a viable alternative for the current CMOS VLSI. This work targets design of logic module in QCA. It reports a modular design methodology to build the fault tolerant 2 n :1 multiplexer with optimized wire-crossings, delay and power consumption. A 2:1 QCA multiplexer is proposed as the basic logic module that in turn is utilized to synthesize 4:1 and 8:1 multiplexers. It shows significant achievement in terms of clock speed (36%), wire-crossing (58%), fault tolerance (77.62%) and power consumption over the existing designs. The effectiveness of proposed multiplexer is further established through synthesis of configurable logic block (CLB) for field programmable gate arrays (FPGAs).

Design of Testable Adder in Quantum‐dot Cellular Automata with Fault Secure Logic

Abstract The rapid advancement of Quantum-dot cellular automata (QCA) technology has moved on to the effective methods for testing these circuits due to its insufficient reliability. The growing demand for fault tolerance and testability attracts more research on it. This paper targets, a novel parity preserving testable adder (t-Adder) in QCA which tackles the internal fault within the gate efficiently resulting a testable circuit. The fault patterns of t-Adder gate under cell deposition defects are investigated. The most striking characteristic of this logic is that it is completely testable for single as well as multiple stuck-at faults using only three test vectors. Also, the functionality and the defect tolerance of the proposed t-Adder under the Path Fault Secure (PFS) scheme are studied which ensures more reliability. A comprehensive power dissipation analysis, as well as structural analysis of the testable logic gates, is performed which signifies the dominance of t-Adder in low power consumption. Further, the programmable feature of t-Adder is utilized to implement an efficient ALU, realizing 10 important functions along with addition operation. The design of QCA layout, as well as functional verification of the proposed design, is performed using the QCADesigner and HDLQ tool respectively whereas the power dissipation is evaluated using QCAPro simulator.

Efficient realization of digital logic circuit using QCA multiplexer

Quantum-dot cellular Automata (QCA), a viable alternative to current CMOS, is gaining its prominence in digital circuit due to its very high device density and clocking speed. This work targets design of efficient logic circuits based on QCA multiplexer. The design capability of the multiplexer in QCA is investigated implementing XOR, XNOR logic gate and arithmetic logic unit. Further, efficient sequential circuits like D latch, T latch, D flip-flop, Scan flip-flop, shift registers are designed using QCA multiplexer. Results obtained supports the fact that the proposed designs achieve significant improvement in terms of device density, cell count as well as clock delay than that of the other previous designs.

Design of fault tolerant majority voter for TMR circuit in QCA

The majority voter plays the core role in the Triple-modular redundancy (TMR) based fault tolerant scheme. This work targets to implement a novel fault tolerant structure of the majority voter for the implementation of TMR using Quantum-dot cellular automata (QCA), a viable alternative nanotechnology to current CMOS VLSI. The proposed fault-tolerant voter circuit itself can tolerate a fault and give error free output by improving the overall systems reliability.

Design of low power 5-input majority voter in quantum-dot cellular automata with effective error resilience

In this paper, a comprehensive study has been done on existing Quantum-dot Ceilular Automata (QCA) 5-input majority voters (MV) which explores that all the previous designs provides poor fault tolerance along with high power consumption and weak cell layout architecture. Also, a novel fault tolerant 5-input MV is designed using QCA tile structure. The proposed design exhibits significant improvement over existing MVs in terms of device area (33%). The fault characterization of the 5-input MV under cell omission and extra cell defects are investigated. The outcome proves that the defect tolerance of the proposed MV is 28% in case of single cell omission defect and 100% in case of single extra cell defect. The physical proof affirms stability of the proposed 5-input MV whereas energy analysis confirms the low power consumption of proposed MV. Moreover, the design capability is investigated realizing a 1-bit Adder and an SR latch.