Bibhash Sen

Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability

The quantum-dot cellular automata have emerged as one of the potential computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. On the other hand, reversible computing promises low power consuming circuits by nullifying the energy dissipation during the computation. This work targets the design of a reversible arithmetic logic unit (RALU) in the quantum-dot cellular automata (QCA) framework. The design is based on the reversible multiplexer (RM) synthesized by compact 2:1 QCA multiplexers introduced in this paper. The proposed reversible multiplexer is able to achieve 100% fault tolerance in the presence of single missing or additional cell defects in QCA layout. Furthermore, the advantage of modular design of reversible multiplexer is shown by its application in synthesizing the RALU with separate reversible arithmetic unit (RAU) and reversible logic unit (RLU). The RALU circuit can be tested for classical unidirectional stuck-at faults using the constant variable used in this design. The experimentation establishes that the proposed RALU outperforms the conventional reversible ALU in terms of programming flexibility and testability. HighlightsA reversible QCA multiplexer logic (RM) is designed from irreversible multiplexer.Results show the effectiveness of the design in terms of cost and testing overhead.Fault testing capability is reported.A complete testable reversible arithmetic logic unit (RALU) is synthesized based on separate module of RAU and RLU.Reliability issue is addressed with modularity.

Design of Efficient Full Adder in Quantum-Dot Cellular Automata

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design.

Fault Tolerant QCA Logic Design With Coupled Majority-Minority Gate

Synthesis of efficient DFT (Design for Testability) logic is of prime importance in robustly testable design of QCA based logic circuits. An ingenious universal QCA gate structure, Coupled Majority-Minority (CMVMIN) gate, realizes majority and minority functions simultaneously in its 2-outputs. This device enables area saving implementation of complex QCA logic. In the current work, we investigate cost effective DFT for QCA designs realized with CMVMIN. The fault effects at the gate outputs due to cell deposition and cell misplacement defects are characterized for concurrent testable circuit design. The effective use of unutilized outputs of CMVMIN gates, realizing a circuit, leads to the proposed fault tolerant design that may not be possible with the conventional gate structures.

Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers

Display Omitted A modular design methodology around multiplexer is designed.This work make a trade-off between modular design and its reliability associated with fault tolerance and energy consumptions.Cascading lower order multiplexer to synthesize higher order multiplexer mitigating wire crossing and delay.Application of proposed design in CLB is also done. With the rapid advancement in very large scale integration (VLSI) technology, it is the utmost necessity to achieve a reliable design with low power consumption. The Quantum dot Cellular Automata (QCA) can be such an architecture at nano-scale and thus emerges as a viable alternative for the current CMOS VLSI. This work targets design of logic module in QCA. It reports a modular design methodology to build the fault tolerant 2 n :1 multiplexer with optimized wire-crossings, delay and power consumption. A 2:1 QCA multiplexer is proposed as the basic logic module that in turn is utilized to synthesize 4:1 and 8:1 multiplexers. It shows significant achievement in terms of clock speed (36%), wire-crossing (58%), fault tolerance (77.62%) and power consumption over the existing designs. The effectiveness of proposed multiplexer is further established through synthesis of configurable logic block (CLB) for field programmable gate arrays (FPGAs).

Realizing Reversible Computing in QCA Framework Resulting in Efficient Design of Testable ALU

Reversible logic is emerging as a prospective logic design style for implementing ultra-low-power VLSI circuits. It promises low-power consuming circuits by nullifying the energy dissipation in irreversible logic. On the other hand, as a potential alternative to CMOS technology, Quantum-dot Cellular Automata (QCA) promises energy efficient digital design with high device density and high computing speed. The integration of reversible logic in QCA circuit is expected to be effective in addressing the issue of energy dissipation at nano scale regime. This work targets the design of reversible ALU (arithmetic logic unit) in QCA framework and proposes a new “Reversible QCA” (RQCA). The primary design focus is on optimizing the number of reversible gates, quantum cost and the garbage outputs that are the most important hindrances in realizing reversible logic. Besides optimization, the fault coverage capability of RQCA under missing/additional cell deposition defects is analysed. The scope of reversible logic is further outstretched by introducing a novel DFT (design for testability) architecture around the reversible ALU that reduces testing overhead. The performance of proposed ALU is evaluated, subjected to different faults, and is established to be more effective than the existing ALU.

Introducing universal QCA logic gate for synthesizing symmetric functions with minimum wire-crossings

This work introduces a universal Quantum-Dot Cellular Automata logic gate (UQCALG) for synthesizing symmetric functions with the target to reduce wire crossings in a design as well as the number of operating clock cycles. It is realized with the coupled majority-minority gate (CMVMIN) structure. The proposed UQCALG structure not only improves performance of a QCA design in terms of wire crossings and clocking, but also the simultaneous access to its four outputs ensures the cost-effective implementation of functions that may not be possible with that of conventional universal logic gates.

An efficient multiplexer in quantum-dot cellular automata

Quantum-dot Cellular Automata (QCA) technology is considered as the alternative to state-of-the-art CMOS due to its extra low-power, extremely dense and high speed structures at nano-scale. This paper proposes a novel design of 2:1 multiplexer in QCA, targeting better area efficiency and reduced input to output delay.

Thresholding using Quantum-dot Cellular Automata

Quantum-dot Cellular Automata(QCA), a promising alternative to CMOS technology, can provide a powerful and efficient computing platform for image processing which has heavy computational requirements. Image thresholding is one such image processing technique that plays a significant role in applications of image segmentation for its intuitive properties and simplicity. This work proposes an efficient architecture to carry out thresholding in image processing. It is developed around QCA technology and provides significant improvement over the existing approach.

Synthesis of Reversible Universal Logic around QCA with Online Testability

Quantum-dot Cellular Automata (QCA) can be a viable technology for CMPs (chip multi-processors) with thousands of processors. The QCA based reversible logic promises energy efficient design of the digital circuits. However, the requirement of excessive logic gates as well as its high defect rate limit the performance of a QCA based design. This work proposes a new approach to synthesize the reversible universal QCA logic gate (RUG) with the target to reduce the garbage outputs as well as the number of logic gates to realise a design simultaneously ensuring the defect tolerance. A concurrent error detection methodology is introduced to support the online testing of a circuit designed around the RUG. The experimental designs establish that the RUG can ensure an energy saving cost effective realization of testable QCA circuits.