Mudit Bhargava

Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS

We demonstrate the efficacy and associated costs of three reliability enhancing techniques for bi-stable PUF designs (SRAM and sense amplifier-based) - directed accelerated aging, multiple evaluations, and activation control. Measured results from a 65nm bulk CMOS full custom PUF testchip demonstrate that these technique are able to reduce the percentage of unreliable bits by up to 40%, 83%, and 71% respectively.

Attack resistant sense amplifier based PUFs (SA-PUF) with deterministic and controllable reliability of PUF responses

Physically Unclonable Functions (PUFs) implement die specific random functions that offer a promising mechanism in various security applications. Stability or reliability of a PUF response is a key concern, especially when the IC containing the PUF is subjected to severe environmental variations. In cryptographic applications, errors in response bits need to be completely corrected and this is often done using costly error correction codes (ECC). In identification and authentication applications however, a complete correction of response bits is not necessary and hence costly ECC schemes can be avoided. On the flip side, a response with faulty bits cannot be post-conditioned by one-way functions, resulting in an increased vulnerability to modeling attacks. We propose a sense amplifier based PUF (SA-PUF) structure that generates random bits with increased reliability, resulting in significantly fewer errors in response bits. This eliminates the need of complex and costly ECC circuitry in cryptographic applications. Further, with the reduced cost of ECC implementation, the use of one-way functions to post-condition the outputs becomes more viable even in identification and authentication applications, thereby increasing their resilience to modeling based attacks. Finally, SA-PUF elements are inherently more resilient to environmental changes as compared to most of the earlier proposed silicon based PUF structures. Simulation data in 65nm bulk CMOS industrial process show that SA-based PUFs have 2.5x-3.5x lower errors compared to other PUF implementations when subjected to similar environmental variations.

Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines

A configurable replica bitline (cRBL) technique for controlling sense-amplifier enable (SAE) timing for small-swing bitline SRAMs is described. Post-silicon selection of a subset of replica bitline driver cells from a statistically designed pool of cells facilitates precise SAE timing. An exponential reduction in timing variation is enabled by statistical selection of driver cells, which can provide 14x reduction in SAE timing uncertainty with 200x less area and power than a conventional RBL with equivalent variation control. We describe the post-silicon test and configuration methodology necessary for cRBLs. To demonstrate the efficacy of the proposed cRBL technique, we present measured results from a 90 nm bulk CMOS 64 kb SRAM testchip.

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS

Physical unclonable functions (PUFs) are primitives that generate high-entropy, tamper resistant bits for use in secure systems. For applications such as cryptographic key generation, the PUF response bits must be highly reliable, consistent across multiple evaluations under voltage and temperature variations. Conventionally, error correcting codes (ECC) have been used to improve response reliability, but these techniques have significant area, power, and delay overheads and are vulnerable to information leakage. In this work, we present a highly-reliable, PUF-based, cryptographic key generator that uses no ECC, but instead uses built-in self-test to determine which PUF bits are reliable and only uses those bits for key generation. We implemented a prototype of the key generator in a 65nm bulk CMOS testchip. The key generator generates 1213 bits in an area of <;50k/μm2 with a measured bit error rate of <; 5 * 10-9 in both the nominal and worst case corners (100k measurements each). This is equivalent to a 128-bit key failure rate of <; 10-6. The system can generate a 128-bit key in 1.15μs. Finally, we present a realization of a “strong”-PUF that uses 128 of these highly reliable bits in conjunction with an Advanced Encryption Standard (AES) cryptographic primitive and has a response time of 40ns and is realized in an area of 84k/μm2.

Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS

Physical Unclonable Functions (PUFs) are security primitives used in a number of security applications like authentication, identification, and secure key generation. PUF implementations are evaluated on their security characteristics (uniqueness, randomness, and reliability), as well as conventional VLSI design metrics (area, power, and performance). We compare bi-stable based PUFs (SRAM and sense amplifiers) and delay based PUFs (arbiter and ring oscillator) using measurements from a testchip in 65nm bulk CMOS. Security metrics are measured on multiple dies and reliability measurements are based on multiple evaluations of PUF circuits across operating voltage (1.0V to 1.4V) and temperature (-20°C to 85°C).

Low-overhead, digital offset compensated, SRAM sense amplifiers

Device variability in modern processes has become a major concern in SRAM design, degrading performance, yield, power, and reliability. While low-swing bitlines can reduce power consumption and increase performance, offset in the sense amplifiers due to device variability hinders the scalability of this technique. A promising method for decreasing the offset is post-silicon tuning using digitally controlled offset compensation. Thus, we have designed and implemented low-overhead, digital offset compensated, SRAM sense amplifiers using both the latch-style and StrongARM topologies. Measured results from a 4mm2 testchip design in a 45nm bulk CMOS process containing 3000 sense amplifier instances per chip show that we can reduce the standard deviation of offset (σOFFSET) by over 5x.

Side-channel attack resistant ROM-based AES S-Box

In the AES algorithm, the Substitution Box (S-Box) often dominates the area and delay of implementations. The S-Box performs a byte-wise substitution on the data based on an established code book, and most AES algorithm implementations use a large complex logic block consisting mainly of XORs to implement the S-Box. Direct implementation of the S-Box with a look-up table (LUT) has been eschewed due to difficulty in pipelining the structure, hence restricting the throughput. However, we present a custom ROM-based S-Box implementation that can achieve comparable throughput to logic-based implementations, yet is smaller in both area and power. Additionally, the symmetrical nature of the ROM is well suited towards achieving data-independent power dissipation, which is key in defending against power analysis side-channel attacks. We present both power-analysis hardened and unhardened ROM-based S-Box designs which significantly outperform logic-based designs in area, power, performance, and power-analysis resistance.

Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers

SRAM design in scaled technologies requires knowledge of phenomena at the process, circuit, and architecture level. Decisions made at various levels of the design hierarchy affect the global figures of merit (FoMs) of an SRAM, such as, performance, power, area, and yield. However, the lack of a quick mechanism to understand the impact of changes at various levels of the hierarchy on global FoMs makes an accurate assessment of SRAM design innovations difficult. Thus, we introduce Virtual Prototyper (ViPro), a tool that helps SRAM designers explore the large design space by rapidly generating optimized virtual prototypes of complete SRAM macros. It does so by allowing designers to describe the SRAM components with varying levels of detail and by incorporating them into a hierarchical model that captures circuit and architectural features of the SRAM to optimize a complete prototype. It generates base-case prototypes that provide starting points for design space exploration, and assesses the impact of process, circuit, and architectural changes on the overall SRAM macro design.

SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states

Physically Unclonable Functions (PUFs) are structures with many applications, including device authentication, identification, and cryptographic key generation. In this paper we propose a new PUF, called SCAN-PUF, based on scan-chain power-up states. We argue that scan chains have multiple characteristics that make them uniquely suited as a low-cost PUF. We present results from test chips fabricated in a 65nm bulk CMOS process in support of these claims. While approximately 20% of the total population of scan elements are unreliable across temperature variations, we find that simple unanimous selection schemes can result in mean error rates of less than 0.1% for the selected populations across all measurements collected.

Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC

The embedded memory hierarchy of microprocessors and systems-on-a-chip plays a critical role in the overall system performance, area, power, resilience, and yield. However, as process technologies scale down to nanometer-regime geometries, the design and implementation of the embedded memory system are becoming increasingly difficult due to a number of exacerbating factors including increasing process variability, manufacturing defects, device wear out, and susceptibility to energetic particle strikes. Consequently, conventional memory resilience techniques will be unable to counter the raw bit error rate of the memory arrays in future technologies at economically feasible design points. Error correcting codes (ECC) are a widely-used and effective technique for correcting memory errors, but using conventional ECC techniques to correct more than one bit per word incurs high latency, area, and power overheads. In this work, we propose a novel ECC scheme based on erasure coding that can extend ECC to correct and detect multiple erroneous bits at low latency, area, and power overheads. Our results show that the increased memory resilience afforded by erasure-based ECC (EB-ECC) can be traded off to boost the memory performance, area, power, and yield. We show that EB-ECC, when combined with less than 5% row redundancy, can improve the cache access latency, power, and stability by over 40% on average, while maintaining near 100% yield and runtime reliability.