Alexander B. Hoefler

Low-overhead, digital offset compensated, SRAM sense amplifiers

Device variability in modern processes has become a major concern in SRAM design, degrading performance, yield, power, and reliability. While low-swing bitlines can reduce power consumption and increase performance, offset in the sense amplifiers due to device variability hinders the scalability of this technique. A promising method for decreasing the offset is post-silicon tuning using digitally controlled offset compensation. Thus, we have designed and implemented low-overhead, digital offset compensated, SRAM sense amplifiers using both the latch-style and StrongARM topologies. Measured results from a 4mm2 testchip design in a 45nm bulk CMOS process containing 3000 sense amplifier instances per chip show that we can reduce the standard deviation of offset (σOFFSET) by over 5x.

An Enhanced Canary-Based System With BIST for SRAM Standby Power Reduction

To achieve aggressive standby power reduction for static random access memory (SRAM), we have previously proposed a closed-loop VDD scaling system with canary replicas that can track global variations. In this paper, we propose several techniques to enhance the efficiency of this system for more advanced technologies. Adding dummy cells around the canary cell improves the tracking of systematic variations. A new canary circuit avoids the possibility that a canary cell may never fail because it resets into its more stable data pattern. A built-in self-test (BIST) block incorporates self-calibration of SRAM minimum standby VDD and the initial failure threshold due to intrinsic mismatch. Measurements from a new 45 nm test chip further demonstrate the function of the canary cells in smaller technology and show that adding dummy cells reduces the variation of the canary cell.