Muhammad A. Elmessary

Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs

The fin-edge roughness (FER) and the TiN metal grain work function (MGW)-induced variability affecting OFF and ON device characteristics are studied and compared between a 10.4-nm gate length In0.53Ga0.47As FinFET and a 10.7-nm gate length Si FinFET. We have analyzed the impact of variability by assessing five figures of merit (threshold voltage, subthreshold slope, OFF-current, drain-induced-barrier-lowering, and ON-current) using the two state-of-the-art in-house-build 3-D simulation tools based on the finite-element method. Quantum-corrected 3-D drift-diffusion simulations are employed for variability studies in the subthreshold region while, in the ON-region, we use quantum-corrected 3-D ensemble Monte Carlo simulations. The In0.53Ga0.47As FinFET is more resilient to the FER and MGW variability in the subthreshold compared with the Si FinFET due to a stronger quantum carrier confinement present in the In0.53Ga0.47As channel. However, the ON-current variability is between 1.1 and 2.2 times larger for the In0.53Ga0.47As FinFET than for the Si counterpart, respectively.

3-D Finite Element Monte Carlo Simulations of Scaled Si SOI FinFET With Different Cross Sections

Nanoscaled Si SOI FinFETs with gate lengths of 12.8 and 10.7 nm are simulated using 3-D finite element Monte Carlo (MC) simulations with 2-D Schrodinger-based quantum corrections. These nonplanar transistors are studied for two cross sections: rectangular-like and triangular-like, and for two channel orientations: (100) and (110). The 10.7-nm gate length rectangular-like FinFET is also simulated using the 3-D nonequilibrium Greens functions (NEGF) technique and the results are compared with MC simulations. The 12.8 and 10.7 nm gate length rectangular-like FinFETs give larger drive currents per perimeter by about 33- 37% than the triangular-like shaped but are outperformed by the triangular-like ones when normalised by channel area. The devices with a (100) channel orientation deliver a larger drive current by about 11% more than their counterparts with a (110) channel when scaled to 12.8 nm and to 10.7 nm gate lengths. ID - VG characteristics obtained from the 3-D NEGF simulations show a remarkable agreement with the MC results at low drain bias. At a high drain bias, the NEGF overestimates the on-current from about VG - VT = 0.3 V because the NEGF simulations do not include the scattering with interface roughness and ionized impurities.

Anisotropic Quantum Corrections for 3-D Finite-Element Monte Carlo Simulations of Nanoscale Multigate Transistors

Anisotropic 2-D Schrödinger equation-based quantum corrections dependent on valley orientation are incorporated into a 3-D finite-element Monte Carlo simulation toolbox. The new toolbox is then applied to simulate nanoscale Si Siliconon-Insulator FinFETs with a gate length of 8.1 nm to study the contributions of conduction valleys to the drive current in various FinFET architectures and channel orientations. The 8.1 nm gate length FinFETs are studied for two cross sections: rectangular-like and triangular-like, and for two channel orientations: 〈100〉 and 〈110〉. We have found that quantum anisotropy effects play the strongest role in the triangular-like 〈100〉 channel device increasing the drain current by ~13% and slightly decreasing the current by 2% in the rectangular-like 〈100〉 channel device. The quantum anisotropy has a negligible effect in any device with the 〈110〉 channel orientation.

Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes

We investigate the performance and scalability of III-V-OI In0.53Ga0.47As and SOI Si FinFETs using state-of-the-art in-house-built 3D simulation tools. Three different technology nodes specified in the ITRS have been analysed with gate lengths (L G) of 14.0 nm, 12.8 and 10.4 nm for the InGaAs FinFETs and 12.8 nm, 10.7 and 8.1 nm for the Si devices. At a high drain bias, the 12.8 and 10.4 nm InGaAs FinFETs deliver 15% and 13% larger on-currents but 14% larger off-currents than the equivalent 12.8 and 10.7 nm Si FinFETs, respectively. For equivalent gate lengths, both the InGaAs and the Si FinFETs have the same I ON/I OFF ratio (5.9 × 104 when L G = 12.8 nm and 5.7 × 104 when L G = 10.4(10.7) nm). A more pronounced S/D tunnelling affecting the InGaAs FinFETs leads to a larger deterioration in their SS (less than 10%) and DIBL (around 20%) compared to the Si counterparts.

FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7- and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 〈110〉 channel orientation is more resilient to the MGG and LER variability in both architectures.

3D Monte Carlo study of scaled SOI FinFETs using 2D Schrödinger quantum corrections

SOI Si FinFETs scaled to gate lengths of 12.8 nm, 10.7 nm and 8.1 nm are simulated using 3D Finite Element Monte Carlo simulations with 2D Schrödinger based quantum corrections considering two cross-sections: rectangular and triangular, with rounded corners, in the preferred (110) channel orientation. The rectangular FinFETs give larger drive currents per perimeter than the triangular FinFETs but are outperformed by the triangular ones when normalised by channel area. In the scaling process, the drive current increases by about 5% (4%) and 5% (1%) for rectangular (triangular) cross-sections with nearly ideal sub-thresholds of 72 (66) mV/dec. The effect of interface roughness increases during the scaling from 3% to 12% and affects stronger the triangular cross-section FinFETs.

Study of strained effects in nanoscale GAA nanowire FETs using 3D Monte Carlo simulations

3D Finite Element ensemble Monte Carlo simulations with integrated 2D Schrödinger Equation quantum corrections are employed to forecast the performance of scaled Si gate-all-around (GAA) nanowire (NW) FETs with unstrained/strained channel. The results from the 3D MC toolbox were compared against experimental I-V characteristics of a 22 nm gate length GAA NW FET with excellent agreement. The NW FET is then scaled to a 10 nm gate length, studying the interplay of the pre-existing quantum confinement in (100) and (110) channel orientations with uniaxial strain engineering, with a strength of 0.5%, 0.7% and 1.0%. We found that increasing the uniaxial strain in the channel is largely limited by the quantum confinement which weakens the strain induced drive current increase to about 7% in the (100) channel and to less than 5% in the (110) channel.

3D MC simulations of strain, channel orientation, and quantum confinement effects in nanoscale Si SOI FinFETs

An in-house 3D Finite Element (FE) Monte Carlo (MC) toolbox is used to study the effects of uniaxial tensile strain in nanoscale Si n-channel SOI FinFETs with two channel orientations ((100) and (110)). We simulate a FinFET with a rectangular-like cross-section (4.5 nm × 11 nm) and a gate length of 8.1 nm with EOT=0.55 nm and study the effects of two types of tensile strain: uniaxial (100) and uniaxial (110) with strain strengths of 0.5%, 0.7% and 1.0%. To show how quantum confinement can degrade the effectiveness of strain engineering, we compare the results with a bigger device with a rectangular-like cross section (12 nm × 30 nm) and a gate length of 25 nm with EOT=1.12 nm. It is found that applying the uniaxial (100) strain increases more the on-current than the uniaxial (110) strain. Moreover, with increasing the strain strength, the quantum confinement induced pre-existing valley splitting starts to weaken the strain effect especially in the (110) channel orientation.

Anisotropic schrodinger equation quantum corrections for 3D Monte Carlo simulations of nanoscale multigate transistors

We incorporated anisotropic 2D Schrodinger equation based quantum corrections (SEQC) that depends on valley orientation into a 3D Finite Element (FE) Monte Carlo (MC) simulation toolbox. The MC toolbox was tested against experimental ID-VG characteristics of the 22 nm gate length GAA Si nanowire (NW) with excellent agreement at both low and high drain biases. We then scaled the Si GAA NW according to the ITRS specifications to a gate length of 10 nm. To show the effect of anisotropic QC on the ID-VG characteristics, we simulate two 8:1 nm gate length FinFETs, rectangular-like (REC) and triangular-like (TRI), with the <;100> and 〈100〉 channel orientations. The QC anisotropy effect is more pronounced in the 〈100〉 channel TRI device increasing the drain current by about 13% and slightly decreasing the current by 2% in the 〈100〉 channel REC device. However, the QC anisotropy has negligible effect in any device in the 〈100〉 orientation.

Multi-subband interface roughness scattering using 2D finite element schodinger equation for monte carlo simulations of multi-gate transistors

Interface roughness scattering (IRS) is one of the key limiting scattering mechanism for both planar and non-planar CMOS devices. To predict the performance of future scaled devices and new structures the quantum mechanical confinement based IRS models are essential. In this work, the in-house 3D finite element Monte Carlo code with 2D Schrodinger equation based quantum correction serves as a base for implementation of a new multi-subband extended Prange & Nee (EPN) IRS model and for comparison with the previously used 3D Ando model. The transistors selected for the comparison are 10.7 nm gate length SOI Si FinFETs with two cross-sections: rectangular and triangular. The drive current for the rectangular device has been reduced by 25% when using the multi-subband EPN model and even more reduced for the triangular shape, by 44%, at VD = 0.7 V.