K. Kalna

Scaling of pseudomorphic high electron mobility transistors to decanano dimensions

The performance enhancement associated with the scaling of pseudomorphic high electron mobility transistors (PHEMTs) to deep decanano dimensions is studied using Monte Carlo (MC) simulations. The full scaling of a standard 120 nm PHEMT to gate lengths of 90, 70, 50 and 30 nm in both lateral and vertical dimensions is compared with an approach where only the lateral dimensions are scaled. The study is based on an extended transport module integrated in the finite element MC simulator H2F and accurate up to an electric field of 200 kV/cm, and on the careful calibration of MC device simulations against I–V characteristics from the real 120-nm gate length PHEMT. The fully scaled devices exhibit a continuous improvement in transconductance as channel lengths reduce while performance deteriorates in devices scaled only laterally. The contact resistances become a limiting factor to the performance of the fully scaled devices at shorter channel lengths. The microwave performance of the scaled devices is studied using the transient MC analysis.

High Mobility III-V MOSFETs For RF and Digital Applications

Developments over the last 15 years in the areas of materials and devices have finally delivered competitive III-V MOSFETs with high mobility channels. This paper briefly reviews the above developments, discusses properties of the GdGaO/ Ga2O3 MOS systems, presents GaAs MOSFET DC and RF data, and concludes with an outlook for high indium content channel MOSFETs. GaAs based MOSFETs are potentially suitable for RF power amplification, switching, and front-end integration in mobile and wireless applications while MOSFETs with high indium content channels are of interest for future CMOS applications.

Effects of Self-Heating on Performance Degradation in AlGaN/GaN-Based Devices

A self-consistent electrothermal transport model that couples electrical and thermal transport equations is established and applied to AlGaN/GaN device structures grown on the following three different substrate materials: 1) SiC; 2) Si; and 3) sapphire. Both the resultant I-V characteristics and surface temperatures are compared to experimental I -V measurements and Raman spectroscopy temperature measurements. The very consistent agreement between measurements and simulations confirms the validity of the model and its numerical rendition. The results explain why the current saturation in measured I-V characteristics occurs at a much lower electric field than that for the saturation of electron drift velocity. The marked difference in saturated current levels for AlGaN/GaN structures on SiC, Si, and sapphire substrates is directly related to the different self-heating levels that resulted from the different biasing conditions and the distinctive substrate materials.

Ballistic transport in Si, Ge, and GaAs nanowire MOSFETs

The influence of various channel materials and crystallographic orientations on the performance of nanowire MOSFETs operating in pure ballistic regime is investigated using 3D quantum-mechanical simulations. We consider three different materials (Si, Ge, GaAs) in nanowire transistors fabricated on a <010>-wafer with an arbitrary channel orientation and provide a better understanding of the transport phenomena that may occur in each device configuration

Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors

An efficient implementation of the density-gradient (DG) approach for the finite element and finite difference methods and its application in drift-diffusion (D-D) simulations is described in detail. The new, second-order differential (SOD) scheme is compatible with relatively coarse grids even for large density variations thus applicable to device simulations with complex 3-D geometries. Test simulations of a 1-D metal-oxide semiconductor diode demonstrate that the DG approach discretized using our SOD scheme can be accurately calibrated against Schrödinger-Poisson calculations exhibiting lower discretization error than the previous schemes when using coarse grids and the same results for very fine meshes. 3-D test D-D simulations using the finite element method are performed on two devices: a 10 nm gate length double gate metal-oxide-semiconductor field-effect transistor (MOSFET) and a 40 nm gate length Tri-Gate fin field-effect transistor (FinFET). In 3-D D-D simulations, the SOD scheme is able to converge to physical solutions at high voltages even if the previous schemes fail when using the same mesh and equivalent conditions. The quantum corrected D-D simulations using the SOD scheme also converge with an atomistic mesh used for the 10 nm double gate MOSFET saving computational resources and can be accurately calibrated against the results from non-equilibrium Greens functions approach. Finally, the simulated ID-VG characteristics for the 40 nm gate length Tri-Gate are in an excellent agreement with experimental data.

Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs

The potential performance of n-type implant-free (IF) III-V nanoMOSFETs with an In0.75Ga0.25As channel is studied using finite-element heterostructure Monte Carlo (MC) and parallel 3D drift-diffusion (D-D) simulations. These devices, scaled to gate lengths of 30, 20, and 15 nm, are compared with the equivalent gate length In0.3Ga0.7As channel IF MOSFETs and with a state-of-the-art Si TriGate FinFET. The benchmarking study is based on careful calibration of the MC simulator against experimental transport data obtained from relevant delta-doped heterostructures with a high-k gate dielectric. At 0.8-V supply voltage, the 30-nm gate length In0.75Ga0.25As channel IF III-V MOSFET is predicted to deliver a drive current of 2880 muA/mum and to have a subthreshold slope of 94.7 mV/dec compared with 2380 muA/mum for an equivalent gate length In0.3Ga0.7As channel IF MOSFET. When the In0.75Ga0.25As channel IF transistor is scaled to 20- and 15-nm gate lengths, the drive current increases to 3520 and 3605 muA/mum, featuring subthreshold slopes of 107.8 and 131.7 mV/dec, respectively. The threshold voltage variability induced by the discrete dopants in the delta-doped plane is studied using 3-D D-D simulations. The 30-, 20-, and 15-nm gate length In0.7Ga0.25As channel IF transistors exhibit threshold voltage standard deviations of 42, 58, and 61 mV, respectively, which are close to or lower than those observed in bulk Si MOSFETs with equivalent gate lengths.

Impact of interface state trap density on the performance characteristics of different III-V MOSFET architectures

Abstract The effect of interface state trap density, D it , on the current–voltage characteristics of four recently proposed III–V MOSFET architectures: a surface channel device, a flat-band implant-free HEMT-like device with δ -doping below the channel, a buried channel design with δ -doping, and implant-free quantum-well HEMT-like structure with no δ -doping, has been investigated using TCAD simulation tools. We have developed a methodology to include arbitrary energy distributions of interface states into the input simulation decks and analysed their impact on subthreshold characteristics and drive current. The distributions of interface states having high density tails that extend to the conduction band can significantly impact the subthreshold performance in both the surface channel design and the implant-free quantum-well HEMT-like structure with no δ -doping. Furthermore, the same distributions have little or no impact on the performance of both flat-band implant-free and buried channel architectures which operate around the midgap.

Quantum Corrections Based on the 2-D Schrödinger Equation for 3-D Finite Element Monte Carlo Simulations of Nanoscaled FinFETs

Solutions of the 2-D Schrödinger equation across the channel using a finite element method have been implemented into a 3-D finite element (FE) ensemble Monte Carlo (MC) device simulation toolbox as quantum corrections. The 2-D FE Schrödinger equation-based quantum corrections are entirely calibration free and can accurately describe quantum confinement effects in arbitrary device cross sections. The 3-D FE quantum corrected MC simulation is based on the tetrahedral decomposition of the simulation domain and the 2-D Schrödinger equation is solved at prescribed transverse planes of the 3-D mesh in the transport direction. We apply the method to study output characteristics of a nonplanar nanoscaled MOSFET, a{10.7}-nm gate length silicon-on-insulator FinFET, investigating 〈100〉 and 〈110〉 channel orientations. The results are then compared with those obtained from 3-D FE MC simulations with quantum corrections via the density gradient method showing very similar I-V characteristics but very different density distributions.

3D Finite Element Monte Carlo Simulations of Multigate Nanoscale Transistors

A 3D ensemble Monte Carlo device simulation tool with quantum corrections based on the tetrahedral decomposition of a simulation domain has been developed for the modeling of electron transport in nonplanar nano-MOSFETs. This 3D tool includes a presimulation drift-diffusion transport model which can also be used separately. A discretization by finite element method can accurately describe a 3D device geometry and speed up complex 3D simulations. The quantum corrections are included via a density gradient approach and the interface roughness via Andos model. ID - VG characteristics of a 25-nm gate length Si silicon-on-insulator (SOI) FinFET, selected as an application example, shows an excellent agreement with experimental data including the subthreshold slope. We show that the device on-current for a (110) channel orientation could be improved by about 15% for a (100) channel orientation. The role of quantization of energy levels affecting the distribution of electron density at sidewalls of the SOI FinFET is found to be different at low (0.05 V) and high (1.0 V) gate biases.

Monte Carlo Simulations of High-Performance Implant Free In

The potential performance of implant free heterostructure In0.3Ga0.7As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a high-kappa dielectric. The MC simulations show that the 30 nm gate length implant free MOSFET can deliver a drive current of 2174 muA/mum at 0.7 V supply voltage. The drive current increases to 2542 muA/mum in the 20 nm gate length device, saturating at 2535 muA/mum in the 15 nm gate length one. When quantum confinement corrections are included into MC simulations, they have a negligible effect on the drive current in the 30 and 20 nm gate length transistors but lower the 15 nm gate length device drive current at 0.7 V supply voltage by 10%. When compared to equivalent Si based MOSFETs, the implant free heterostructure MOSFETs can deliver a very high performance at low supply voltage, making them suitable for low-power high-performance CMOS applications