Muhammad K. Dhodhi

Datapath synthesis using a problem-space genetic algorithm

This paper presents a new approach to datapath synthesis based on a problem-space genetic algorithm (PSGA). The proposed technique performs concurrent scheduling and allocation of functional units, registers, and multiplexers with the objective of finding both a schedule and an allocation which minimizes the cost function of the hardware resources and the total time of execution. The problem-space genetic algorithm based datapath synthesis system (PSGA-Synth) combines a standard genetic algorithm with a known heuristic to search the large design space in an intelligent manner. PSGA-Synth handles multicycle functional units, structural pipelining, conditional code and loops, and provides a mechanism to specify lower and upper bounds on the number of control steps. The PSGA-Synth was tested on a set of problems selected from the literature, as well as larger problems created by us, with promising results. PSGA-Synth not only finds the best known results for all the test problems examined in a relatively small amount of CPU time, but also has the ability to efficiently handle large problems. >

Multiprocessor scheduling in a genetic paradigm

Abstract In this paper, we present a technique based on the problem-space genetic algorithm (PSGA) for the static scheduling of directed acyclic graphs onto homogeneous multiprocessor systems to reduce the response-time. The PSGA based approach combines genetic algorithms with a list scheduling heuristic to search a large solution space efficiently and effectively to find the best possible solution in an acceptable cpu time. Comparison of results with the genetic algorithm (GA) based scheduling technique for the Stanford manipulator and the Elbow manipulator examples shows a significant improvement in the response-time. We also demonstrate the effectiveness of our algorithm by comparing it with the Critical Path/Maximum Immediate Successor First (CP/MISF) list scheduling technique for randomly generated graphs. The proposed scheme offers on the average a 3.6% improvement in the response-time as compared to the CP/MISF technique for all the random graphs.

D-ISODATA

With the advent of high-speed networks and the availability of powerful high-performance workstations, network of workstations has emerged as the most cost-effective platform for computation-intensive applications. One of the major applications for the network of workstations is in the field of remote sensing, where because of the high dimensionality of data, most of the existing data exploitation procedures are computation-intensive. To test the utility of the network of workstations in the field of remote sensing we have adopted a modified version of the well-known ISODATA classification procedure which may be considered as the benchmark for all unsupervised classification algorithms. The ISODATA algorithm is an iterative method that uses Euclidean distance as the similarity measure to cluster data elements into different classes. We have designed and developed a distributed version of ISODATA algorithm (D-ISODATA) on the network of workstations under a message-passing interface environment and have obtained promising speedup. To reduce the processing load and thereby increase the throughput, the ISODATA procedure is commonly applied to only the first few principal component images derived from the original set of the multispectral images. The drawback with the principal component approach is that it is based entirely on the statistical significance of the spectra, rather than the uniqueness of the individual spectra. As, small objects and ground features would likely manifest themselves in the last principal component images, that is, eigen images, discarding them prior to classification would lead to the loss of valuable information. The significant enhancement in processing speed on the network of workstations makes it possible for us to apply our distributed algorithm D-ISODATA to the entire set of multispectral images directly, thereby preserving all the spectral signatures in the data, regardless of their statistical significance.

Task assignment using a problem‐space genetic algorithm

The task assignment problem is one of assigning tasks of a parallel program among the processors of a distributed computing system in order to reduce the job turnaround time and to increase the throughput of the system. Since the task assignment problem is known to be NP-complete except in a few special situations, satisfactory suboptimal solutions obtainable in a reasonable amount of computation time are generally sought. In the paper we introduce a technique based on the problem-space genetic algorithm (PSGA) for the static task assignment problem in both homogeneous and heterogeneous distributed computing systems to reduce the task turnaround time and to increase the throughput of the system by properly balancing the load and reducing the interprocessor communication time among processors. The PSGA based approach combines the power of genetic algorithms, a global search method, with a simple and fast problem-specific heuristic to search a large solution space efficiently and effectively to find the best possible solution in an acceptable CPU time. Experimental results on test examples from the literature show considerable improvements in both the assignment cost and the CPU times over the previous work. The proposed scheme is also applied to a digital signal processing (DSP) system consisting of 119 tasks to illustrate its balancing properties and computational advantage on a large system. The proposed scheme offers 12–30% improvement in the assignment cost as compared to the previous best known results for the DSP example.

SHEMUS: synthesis of heterogeneous multiprocessor systems

Abstract Current VLSI technology enables the implementation of a complicated system on a single chip at a low cost. Thus it has become cost effective to design special-purpose multiprocessor architectures for computationally intensive applications in signal processing, control of power systems and robotics. This paper presents a strategy, designated as SHEMUS, for the synthesis of application-specific heterogeneous multiprocessor systems to meet the various cost and performance constraints. SHEMUS combines a known fast heuristic with a standard genetic algorithm to search a large design space efficiently and effectively. The effectiveness of our technique is demonstrated by comparing it with some existing systems. The proposed strategy provides considerable improvements in the cpu times for reasonable sized problems over previous work.

Task assignment in distributed computing systems

We introduce a technique based on the problem-space genetic algorithm (PSGA) for the static task assignment problem in homogeneous distributed computing systems to reduce the task turnaround time and to increase the throughput of the system by properly balancing the load and reducing the interprocessor communication time among processors. The PSGA based approach combines the power of genetic algorithms, a global search method, with simple and fast problem-specific heuristic to search a large solution space efficiently and effectively to find the best possible solution in an acceptable cpu time. The proposed scheme is applied to a digital signal processing (DSP) system consisting of 119 tasks to illustrate its balancing properties and computational advantage on a large system. The proposed scheme offers 12%-30% improvement in the assignment cost as compared to the previous best known results for the DSP example.<<ETX>>

Assignment and allocation of highly testable data paths under scan optimization

Abstract This paper addresses the synthesis of highly testable data paths under scan optimization from a given scheduled data flow graph. The synthesis uses an intelligent register allocation technique to minimize the number of sequential loops. Sequential loops in a data path cause poor testability and the complexity of test generation grows exponentially with the number of sequential loops. The register allocation technique also identifies certain registers in the synthesized data path as scan registers to break the sequential loops. The synthesis also uses an interconnect allocation scheme which optimizes for the number of multiplexer inputs. Our main objective is to eliminate or minimize the number of sequential loops and to identigy minimum number of scan registers to break these loops. Thus, the synthesized data path is free of sequential loops, highly testable and has a low scan register cost overhead. Our technique is verified on different benchmark examples and the results are promising.

Design-Space Exploration for High-Level Synthesis

The design methodology presented in this paper simultaneously performs scheduling, allocation and module selection using problem-space genetic algorithm (PSGA) to optimize the three items: (1) the hardware resources (i.e., functional units, registers, and interconnection cost), (2) the number of control steps and (3) the length of the clock period. The proposed PSGA based approach uses the inherent parallelism provided by genetic algorithms and exploits the problem-specific knowledge by using a simple and fast heuristic to search a large design space effectively and efficiently. The proposed PSGA method offers several advantages such as the versatility, simplicity, objective independence and the computational advantages for problems of large size over other existing techniques. Experiments on benchmarks show very promising results.

On the m-way graph partitioning problem

The m-way graph partitioning problem (GPP) is an intractable combinatorial optimization problem with many important applications in the design automation of VLSI circuits and in the mapping problem for distributed computing systems. In this paper, we introduce a technique based on a problem-space genetic algorithm (PSGA) for the GPP to reduce the weighted cut-size while keeping the size of each subset balanced. The proposed PSGA based approach integrates a problem-specific simple and fast heuristic with a genetic algorithm to search a large solution space efficiently and effectively to find the best possible solution in an acceptable CPU time. Experimental study shows that our technique produces better results with respect to both the quality of the solution and the computational time over the previous work. The PSGA is a simple, versatile and a generic optimization technique which can also be applied to other combinatorial optimization problems.

Hardware/software codesign in the Estelle and VHDL environments

Abstract Modern industrial high-speed protocols and networks require the use of communication controllers that must handle severe real-time constraints. It will become increasingly difficult to implement them entirely in software, because their implementations would be too slow and offer unacceptable delays. Unfortunately, presently, a big gap exists between the software and hardware development environments which makes it hard to analyze the overall system specifications and performance. In this paper, we attempt to contribute to the integration between these two environments using two standard specification techniques: Estelle and VHDL, the former for distributed systems and the latter for hardware system components. We introduce the basis for a translation system from Estelle to VHDL specifications. We also illustrate the application of our translation rules to a protocol example.