Muhammad Shakeel Qureshi

Single chip CMUT arrays with integrated CMOS electronics: Fabrication process development and experimental results

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach maximizes transducer sensitivity by minimizing parasitic capacitances and ultimately improves the signal to noise ratio. Additionally, due to physical size limitations required for catheter based imaging devices, optimization of area occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication of CMUTs on custom designed CMOS electronics from a commercial IC foundry. This is achieved by modifying a low temperature micromachining process by adding one additional mask and developing a sloped wall dry etching step on isolation oxide layer for metal interconnect. Experiments show that both the CMUT and the integrated CMOS electronics are functional, resulting combination generating pulse-echo response suitable for ultrasound imaging.

A large-scale Reconfigurable Smart Sensory Chip

The Reconfigurable Smart Sensory Chip (RSSC) is a powerful tool for fast prototyping sensory microsystems. Innovative design ideas can be quickly realized and tested in hardware without doing time-consuming and expensive silicon fabrication. The RSSC is a large-scale floating-gate based IC containing 8 universal sensor interface blocks, each of which can be configured for voltage sensing, capacitive sensing, or current sensing, and 28 configurable analog blocks. The outputs of the interface circuits can be multiplexed out in a time-division sequence or can be routed to the configurable analog blocks for further analog signal processing or data conversion. With more than 50,000 programmable elements and on-chip programming circuitry, RSSC is an extremely powerful tool to develop and test a great variety of smart sensory microsystems in minutes.

P0-18 Forward-Looking IVUS Imaging Using a Dual-Annular Ring CMUT Array: Experimental Results

This paper presents the experimental results on forward-looking intravascular ultrasound (FL-IVUS) using dual- annular-ring CMUT arrays. The array has a diameter of 1mm including bondpads which consists of separate, concentric 24 transmit and 32 receive ring arrays built on the same silicon substrate. This configuration has the potential for independent optimization of each array and uses the silicon area more effectively without any drawback. For imaging experiments, we designed and constructed a custom integrated circuit using a standard 0.5mum CMOS process for data acquisition. A sample pulse-echo signal received from the oil-air interface (plane reflector) at 6 mm had a center frequency of 11 MHz with 95*% fractional 6-dB bandwidth. The measured SNR of the echo was 24 dB with no averaging. B-scan image of a wire-phantom was generated to test the resolution.

High SNR capacitive sensing transducer

This paper describes a high signal-to-noise ratio capacitive sensing transducer with high power efficiency and high area efficiency. The circuit is an example of capacitive circuit and is based on a capacitive feedback charge amplifier. 78.6dB SNR in audio band is achieved with less than 0.5 muW power consumption by making use of a floating-gate transistor. This design gives us the flexibility of controlling the charge on the floating node. The microphone sensor is interfaced with the amplifier to measure the performance of the transducer

PS-15 Floating-Gate Based CMUT Sensing Circuit Using Capacitive Feedback Charge Amplifier

This paper describes the use of a floating-gate based capacitive feedback charge amplifier as a receive circuit for CMUT and investigates the charging effects. Detailed analysis of the capacitive sensing charge amplifier along with a floating-node charge adaptation circuit is presented. Compared with conventional approaches, using a charge amplifier, instead of a transimpedance amplifier, to detect capacitance variation avoids the dilemma of sensitivity-bandwidth trade-off. A version of the capacitive sensing charge amplifier is fabricated in a 0.5 mum CMOS process. The chip contains a 8-to-1 multiplexer and is interfaced with a CMUT annular-ring array, which is designed for forward-looking intravascular ultrasound imaging applications. Pulse-echo experiment is performed in an oil bath using a planar target 3 mm away from the array and the measurement result shows the signal-to-noise ratio of 16.65 dB with 122 muW power consumption around 3 MHz. In another implementation, channel hot electron (CHE) injection and Fowler-Nordheim tunneling currents are used to adjust the charge on the floating node and stabilize the output voltage. By using open-loop configuration, the leakage current of a CMUT device is characterized

A Floating-gate Based Low-Power Capacitive Sensing Interface Circuit

This paper describes a high signal-to-noise ratio capacitive sensing circuit topology based on a capacitive feedback charge amplifier with high power and area efficiency. When the circuit is used in an audio MEMS sensor, 78.6dB SNR in audio band is measured with less than 0.5 muW power consumption. With a MOS-BJT pseudo-resistor feedback scheme, this topology has also been applied to a capacitive micromachined ultrasonic transducer (CMUT) operating around 1MHz. An adaptation scheme using Fowler-Nordheim tunneling and channel hot electron injection mechanisms is also employed to stabilize the output DC voltage in an audio MEMS microphone sensor. The measured noise spectrums show that this slow-time scale adaptation does not degrade the performance of the circuit. Therefore, this simple topology can be employed in many capacitive sensing applications and can achieve high performance with high efficiency

Low-voltage floating-gate CMOS buffer

This paper describes an implementation of a low-voltage CMOS buffer employing a negative feedback to improve its performance. Floating-gate transistors are incorporated to obtain low-threshold transistors and to increase the input/output voltage swing of the circuit operating at 1.2V. The designed circuit is fabricated in 0.5mum CMOS process, and occupies 0.0214mm2. It achieves total harmonic distortion (THD) of 48dB for 10kHz 0.6Vpp sinusoidal input signal

70 MHz CMOS gm-C IF filter

The implementation of a high dynamic range on-chip 70 MHz gm-C filter for a UMTS (WCDMA) superheterodyne receiver is described. The filter is designed in National Semiconductors 0.18 micron standard CMOS process. The Chebyshev approximation is used to implement a 6th order filter in active gm-C. Positive feedback is used to realize a large quality factor (Q). The filter provides blocker attenuation with dynamic range (DR) of 42 dB and with power consumption of 21.78 mW.

SiGe HBT power amplifier for IS-95 CDMA using a novel process, voltage, and temperature insensitive biasing scheme

A novel bias current circuitry for SiGe HBT power amplifier which achieves highly predictable stable current under process, voltage, and temperature (PVT) variations is described in this paper. This approach is ideal for mobile applications under extreme operating conditions. The design offers temperature coefficient of 15.7 ppm//spl deg/C and enables the stabilization of efficiency and output power with ease. The concept was applied to a dual stage power amplifier designed for IS-95 CDMA standard. Maximum linear output power of 28.2 dBm with a gain of 28 dB at 2.5V supply voltage was achieved. The power amplifier has shown a very good stable performance under process, supply voltage, and temperature variations.

Integrated low voltage and low power CMOS circuits for optical sensing of diffraction based micromachined microphone

We present CMOS electronics for optical sensing of diffraction based micromachined microphone. Peak detector and track and hold circuits are used for continuous time approach with only 58 μA of current for 65dB peak SNR (lPa at 1kHz). We also present a 1-bit sigma delta interface ADC for directly digitizing the signal for digital processing with 63 μA of current for 62dB peak SNR (lPa @ 1kHz). The electronics are designed in 0.35um standard digital CMOS process with reduced supply of 1.5Volts. All the analog front end circuits operate in weak inversion with rail-to-rail wide input linear range.