Muhammad Usman Karim Khan

An adaptive complexity reduction scheme with fast prediction unit decision for HEVC intra encoding

The next-generation High Efficiency Video Coding (HEVC) standard aims at providing double compression compared to the state-of-the-art H.264/AVC standard. However, this improved compression efficiency accompanies high computational complexity, which is primarily due to the recursive nature of the Coding Tree Unit structure and complex Rate-Distortion (RD) Optimization of Prediction Units (PU). In this paper, we propose a content-driven adaptive complexity reduction scheme that employs an a priori PU size selection algorithm. We adaptively combine smaller PUs into larger PUs depending upon the video frame contents under consideration. Our scheme eliminates the need for recursive or iterative RD cost comparisons to select the best PU size for an HEVC intra encoder. Experimental results demonstrate that the proposed scheme provides significant time savings (on average 43.74 %) for HEVC intra encoding, while incurring an insignificant video quality loss (on average -0.048 dB BD-PSNR).

Hardware-software collaborative complexity reduction scheme for the emerging HEVC intra encoder

High Efficiency Video Coding (HEVC/H.265) is an emerging standard for video compression that provides almost double compression efficiency at the cost of major computational complexity increase as compared to current industry-standard Advanced Video Coding (AVC/H.264). This work proposes a collaborative hardware and software scheme for complexity reduction in an HEVC Intra encoding system, with run-time adaptivity. Our scheme leverages video content properties which drive the complexity management layer (software) to generate a highly probable coding configuration. The intra prediction size and direction are estimated for the prediction unit which provides reduced computational-complexity. At the hardware layer, specialized coprocessors with enhanced reusability are employed as accelerators. Additionally, depending upon the video properties, the software layer administers the energy management of the hardware coprocessors. Experimental results show that a complexity reduction of up to 60 % and the energy reduction up to 42 % are achieved.

Wild Plant Assessment for Heavy Metal Phytoremediation Potential along the Mafic and Ultramafic Terrain in Northern Pakistan

This study investigates the wild plant species for their phytoremediation potential of macro and trace metals (MTM). For this purpose, soil and wild plant species samples were collected along mafic and ultramafic terrain in the Jijal, Dubair, and Alpuri areas of Kohistan region, northern Pakistan. These samples were analyzed for the concentrations of MTM (Na, K, Ca, Mg, Fe, Mn, Pb, Zn, Cd, Cu, Cr, Ni, and Co) using atomic absorption spectrometer (AAS-PEA-700). Soil showed significant (P < .001) contamination level, while plants had greater variability in metal uptake from the contaminated sites. Plant species such as Selaginella jacquemontii, Rumex hastatus, and Plectranthus rugosus showed multifold enrichment factor (EF) of Fe, Mn, Cr, Ni, and Co as compared to background area. Results revealed that these wild plant species have the ability to uptake and accumulate higher metals concentration. Therefore, these plant species may be used for phytoremediation of metals contaminated soil. However, higher MTM concentrations in the wild plant species could cause environmental hazards in the study area, as selected metals (Fe, Mn, Cr, Ni, Co, and Pb) have toxicological concerns.

Software architecture of High Efficiency Video Coding for many-core systems with power-efficient workload balancing

The High Efficiency Video Coding (HEVC) standard aims at providing ~50% better compression compared to its predecessor (H.264) at the cost of high computational complexity. To enable HEVC video encoding in real-time scenarios, special coding support for parallelization is provided in HEVC that can be exploited by many-core systems. In this work, we present a HEVC software architecture where a video frame is adaptively divided into independent video frame regions (i.e. so-called video tiles) which are processed concurrently on multiple cores. By balancing the workload of each video tile mapped to a particular core, the total power consumption of a system is reduced (through dynamically scaling the operating frequency) under a given frame-rate constraint. We also exploit user tolerance to further curtail the HEVC workload with insignificant video quality degradation. Experimental results illustrate that the proposed approach results in ~43% power savings on a many-core system.

Power efficient and workload balanced tiling for parallelized high efficiency video coding

The increased workload of the High Efficiency Video Coding (HEVC) and processing of high resolution videos require parallelization of the encoding/decoding process. However, to efficiently utilize the hardware resources and power budgets in a many-core processor, workload balanced parallelization of HEVC encoding is of high importance. Further, minimizing the number of active cores for processing the given HEVC encoding workload is required to decrease the power consumption. In order to address the above challenges, this work presents a HEVC parallelization technique to adaptively determine the Tile partitioning while accounting for the compute capabilities of the underlying processing cores. Afterwards, it determines a mapping of Tiled-HEVC processing on different cores such that the number of compute cores is minimized, and hence reducing the power consumption. Experimental results demonstrate that in addition to reducing the total compute cores, our technique provides up to 14.4% power savings compared to state-of-the-art uniform Tile partitioning approach.

An adaptive workload management scheme for HEVC encoding

Managing the complexity of the emerging HEVC standard is a matter of academic and industrial research since its earlier versions. The sophisticated and computation-intensive tools involved in the encoding process must be leveraged if real-time applications are considered. In this paper, we propose a workload management scheme for dynamically controlling the computational complexity of HEVC, under user-defined operation frequency and target FPS. Our scheme receives these two parameters as input and aims to meet the target FPS by adjusting different encoding parameters during execution time. Experiments demonstrate that our scheme successfully meets the target FPS while introducing negligible rate-distortion losses. A comparison with state-of-the-art shows that our scheme is capable of achieving a time reduction of up to 43% for Full HD sequences, with a maximum loss of 0.03 dB in Y-PSNR and a 3.5% increase in bitrate.

A Swift and Memory Efficient Hough Transform for Systems with Limited Fast Memory

This paper focuses on implementation of a speedy Hough Transform (HT) which considers the memory constraints of the system. Because of high memory demand, small systems (DSPs, tiny robots) cannot realize efficient implementation of HT. Keeping this scenario in mind, the paper discusses an effective and memory-efficient method of employing the HT for extraction of line features from a gray scale image. We demonstrate the use of a circular buffer for extraction of image edge pixels and store the edge image in a manner that is different from the conventional way. Approximation of the two dimensional Hough Space by a one dimensional array is also discussed. The experimental results reveal that the proposed algorithm produces better results, on small and large systems, at a rapid pace and is economical in terms of memory usage.

Fast hierarchical intra angular mode selection for high efficiency video coding

In this work, we address the complexity of the most time consuming module of High Efficiency Video Coding (HEVC) Intra-encoding, i.e. the Intra prediction generation. We reduce the computational complexity by estimating the candidates list (most probable Intra prediction modes), using content- and priority-driven gradient detection and hierarchically gathering the results of previous computations. This complexity reduction scheme is adaptive and can be controlled, depending upon the requirements, e.g. frame rate and video quality. On average, our scheme is capable of delivering 44% more time savings than the state-of-the-art scheme for fast Intra mode estimation.

AMBER: adaptive energy management for on-chip hybrid video memories

The ever increasing leakage power of memories in a system has motivated researches for exploiting unconventional memory architectures. Non-Volatile Memory (NVM) used in conjunction with the conventional on-chip SRAMs has given birth to the hybrid memory paradigm, which can be intelligently exploited to reduce the energy consumption while tackling the high read and write latencies of NVMs. We present a novel scheme AMBER that aims at minimizing the total memory energy consumption of a video processing system by leveraging the application-specific properties and distinct latency and power properties of different memory types. AMBER also features architectural support for data-fetching from external memory and adaptively filling the different on-chip memories. We employ AMBER in the next-generation High Efficiency Video Coding (HEVC) standard to minimize the energy consumption of the new complex motion prediction process. Experimental results demonstrate that our AMBER scheme achieves significant energy savings (average 43%) for the on-chip memory.

Hierarchical power budgeting for Dark Silicon chips

The emerging Dark Silicon limitation has led the application designers to carefully consider the available Thermal Design Power (TDP) budgets, hardware resources, and software characteristics. In this paper, we propose a hierarchical scheme for distributing the resources and TDP budget among concurrently executing applications with multi-threaded workloads under throughput constraints. Afterwards, the application-level TDP budget is partitioned among its threads depending upon their workloads, which can then be fine-tuned at run time considering workload variations. We evaluate our scheme for the next-generation, multi-threaded, High Efficiency Video Codec and demonstrate that up to 30.86% higher throughput is achieved compared to the state-of-the-art.