Muhammed Ahosan Ul Karim

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.

BSIM6: Analog and RF Compact Model for Bulk MOSFET

BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node.

Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs

In this letter, we present a thermal network extraction methodology to characterize self-heating effect using two-port RF measurements. We show the technique of determining isothermal condition using only the self-heating (thermal) dominated range of the spectrum. We use a self-consistent self-heating extraction scheme using both the real and imaginary parts of drain port admittance parameters. Appropriate thermal network is investigated, and a large amount of temperature rise due to self-heating is confirmed for short channel silicon-on-insulator MOSFETs with ultrathin body and buried oxide.

Gravure-Printed Sol-Gels on Flexible Glass: A Scalable Route to Additively Patterned Transparent Conductors.

Gravure printing is an attractive technique for patterning high-resolution features (<5 μm) at high speeds (>1 m/s), but its electronic applications have largely been limited to depositing nanoparticle inks and polymer solutions on plastic. Here, we extend the scope of gravure to a new class of materials and on to new substrates by developing viscous sol-gel precursors for printing fine lines and films of leading transparent conducting oxides (TCOs) on flexible glass. We explore two strategies for controlling sol-gel rheology: tuning the precursor concentration and tuning the content of viscous stabilizing agents. The sol-gel chemistries studied yield printable inks with viscosities of 20-160 cP. The morphology of printed lines of antimony-doped tin oxide (ATO) and tin-doped indium oxide (ITO) is studied as a function of ink formulation for lines as narrow as 35 μm, showing that concentrated inks form thicker lines with smoother edge morphologies. The electrical and optical properties of printed TCOs are characterized as a function of ink formulation and printed film thickness. XRD studies were also performed to understand the dependence of electrical performance on ink composition. Printed ITO lines and films achieve sheet resistance (Rs) as low as 200 and 100 Ω/□, respectively (ρ≈2×10(-3) Ω-cm) for single layers. Similarly, ATO lines and films have Rs as low as 700 and 400 Ω/□ with ρ≈7×10(-3) Ω-cm. High visible range transparency is observed for ITO (86-88%) and ATO (86-89%). Finally, the influence of moderate bending stress on ATO films is investigated, showing the potential for this work to scale to roll-to-roll (R2R) systems.

Exploitation of the coffee-ring effect to realize mechanically enhanced inkjet-printed microelectromechanical relays with U-bar-shaped cantilevers

We report a mechanically enhanced inkjet-printed microelectromechanical (MEM) relay with a U-bar-shaped cantilever by exploiting the coffee-ring effect. The printed cantilever shape, especially the effective thickness caused by the elevated walls, can be controlled during the drying process by outward convective flow of silver nanoparticles. This enhances mechanical stiffness to efficiently produce a strongly suspended cantilever that is immune to collapse- and curling-related failures. This approach to enhancing cantilever stiffness is unique to printing-based processes using metal-nanoparticle inks and is not feasible for conventional photolithography processes. The resulting printed MEM relays show a pull-in voltage of only 6.6 V and an on/off ratio of 108 with extremely low on-state resistance (∼14.3 Ω) and off-state leakage that is comparable to those of conventional silicon-based MEM relays.

Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.

Phenomenological Compact Model for QM Charge Centroid in Multigate FETs

We present a phenomenological compact model of the inversion charge centroid considering both the structural and electrical confinements in multigate FETs. The developed new model shows a good match with Technology-CAD (TCAD) data for both physical parameters such as fin thickness in FinFET and wire radius in cylindrical FET, channel doping, and electrical bias variation. With the introduction of fitting parameters, the model is capable of handling hole and electron carriers, various channel materials, and process variations, such as fin shape, etc.

High-Performance Inkjet-Printed Four-Terminal Microelectromechanical Relays and Inverters

We report the first demonstration of inkjet-printed 4-terminal microelectromechanical (MEM) relays and inverters with hyper-abrupt switching that exhibit excellent electrical and mechanical characteristics. This first implementation of a printed 4-terminal device is critically important, since it allows for the realization of full complementary logic functions. The floated fourth terminal (body electrode), which allows the gate switching voltage to be adjusted, is bonded to movable channel beams via a printed epoxy layer in a planar structure, which can move downward together via the electrostatic force between the gate electrodes and body such that the channel can also actuate downward and touch the drain electrode. Because the body, channel, and drain electrodes are completely electrically separated, no detectable leakage or electrical interference between the electrodes is observed. The printed MEM relay exhibited an on-state resistance of only 3.48 Ω, immeasurable off-state leakage, subthreshold swing <1 mV/dec, and a stable operation over 10(4) cycles with a switching delay of 47 μs, and the relay inverter exhibits abrupt transitions between on/off states. The operation of the printed 4-terminal MEM relay was also verified against the results of a 3-dimensional (3D) finite element simulation.

Analysis and modeling of vertical non-uniform doping in bulk MOSFETs for circuit simulation

We present an efficient approach to model the effects of vertical non-uniform doping in bulk MOSFETs. The impact of vertical non-uniform doping on device characteristics is analyzed through systematic TCAD simulations. The qualitative nature of the observed effects is also confirmed by the experimental data available in the literature. A modeling methodology for these effects is developed on BSIM6 model framework. The proposed model is in good agreement with the TCAD simulations.

Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology

The aggressive downscaling of advanced bulk CMOS technologies demands MOSFET models that are able to describe accurately the behavior of devices accounting for all the physical phenomena. A reliable model should have the ability to handle all the different operating regions of the MOS transistor in the whole geometry range of one technology. Targeting to meet the aforementioned needs, the new charge-based compact model BSIM6 has been developed. In this article, as a first benchmarking of BSIM6, the model is evaluated for its scaling capabilities when a single set of parameters is used. The model is compared against a state-of-the-art 40nm CMOS technology. The results attest the models scalability under all bias conditions, proving its reliability for nowadays complex IC designs.