Ali M. Niknejad

Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs

Silicon integrated circuit spiral inductors and transformers are analyzed using electromagnetic analysis. With appropriate approximations, the calculations are reduced to electrostatic and magnetostatic calculations. The important effects of substrate loss are included in the analysis. Classic circuit analysis and network analysis techniques are used to derive two-port parameters from the circuits. From two-port measurements, low-order, frequency-independent lumped circuits are used to model the physical behavior over a broad-frequency range. The analysis is applied to traditional square and polygon inductors and transformer structures as well as to multilayer metal structures and coupled inductors. A custom computer-aided-design tool called ASITIC is described, which is used for the analysis, design, and optimization of these structures. Measurements taken over a frequency range from 100 MHz to 5 GHz show good agreement with theory.

Millimeter-wave CMOS design

This paper describes the design and modeling of CMOS transistors, integrated passives, and circuit blocks at millimeter-wave (mm-wave) frequencies. The effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak f/sub max/ of 135 GHz has been achieved with optimal device layout. The inductive quality factor (Q/sub L/) is proposed as a more representative metric for transmission lines, and for a standard CMOS back-end process, coplanar waveguide (CPW) lines are determined to possess a higher Q/sub L/ than microstrip lines. Techniques for accurate modeling of active and passive components at mm-wave frequencies are presented. The proposed methodology was used to design two wideband mm-wave CMOS amplifiers operating at 40 GHz and 60 GHz. The 40-GHz amplifier achieves a peak |S/sub 21/| = 19 dB, output P/sub 1dB/ = -0.9 dBm, IIP3 = -7.4 dBm, and consumes 24 mA from a 1.5-V supply. The 60-GHz amplifier achieves a peak |S/sub 21/| = 12 dB, output P/sub 1dB/ = +2.0 dBm, NF = 8.8 dB, and consumes 36 mA from a 1.5-V supply. The amplifiers were fabricated in a standard 130-nm 6-metal layer bulk-CMOS process, demonstrating that complex mm-wave circuits are possible in todays mainstream CMOS technologies.

An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers

An ultrawideband 3.1-10.6-GHz low-noise amplifier employing an input three-section band-pass Chebyshev filter is presented. Fabricated in a 0.18-/spl mu/m CMOS process, the IC prototype achieves a power gain of 9.3 dB with an input match of -10 dB over the band, a minimum noise figure of 4 dB, and an IIP3 of -6.7 dBm while consuming 9 mW.

A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry

This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1 m wireless link at 4 Gb/s QPSK with less than 10-11 BER.

A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration

A 1.8-GHz LC VCO designed in a 0.18-/spl mu/m CMOS process achieves a very wide tuning range of 73% and measured phase noise of -123.5 dBc/Hz at a 600-kHz offset from a 1.8-GHz carrier while drawing 3.2 mA from a 1.5-V supply. The impacts of wideband operation on start-up constraints and phase noise are discussed. Tuning range is analyzed in terms of fundamental dimensionless design parameters yielding useful design equations. An amplitude calibration technique is used to stabilize performance across the wide band of operation. This amplitude control scheme not only consumes negligible power and area without degrading the phase noise, but also proves to be instrumental in sustaining the VCO performance in the upper end of the frequency range.

Design considerations for 60 GHz CMOS radios

With the availability of 7 GHz of unlicensed spectrum around 60 GHz, there is a growing interest in using this resource for new consumer applications requiring very high-data-rate wireless transmission. Historically, the cost of the 60 GHz electronics, implemented in the compound semiconductor technology, has been prohibitively expensive. A fully integrated CMOS solution has the potential to drastically reduce costs enough to hit consumer price points. System, circuit, and device-level barriers to a low-cost 60 GHz CMOS implementation are described, potential solutions are explored, and remaining challenges are discussed.

Extremely bendable, high-performance integrated circuits using semiconducting carbon nanotube networks for digital, analog, and radio-frequency applications

Solution-processed thin-films of semiconducting carbon nanotubes as the channel material for flexible electronics simultaneously offers high performance, low cost, and ambient stability, which significantly outruns the organic semiconductor materials. In this work, we report the use of semiconductor-enriched carbon nanotubes for high-performance integrated circuits on mechanically flexible substrates for digital, analog and radio frequency applications. The as-obtained thin-film transistors (TFTs) exhibit highly uniform device performance with on-current and transconductance up to 15 μA/μm and 4 μS/μm. By performing capacitance-voltage measurements, the gate capacitance of the nanotube TFT is precisely extracted and the corresponding peak effective device mobility is evaluated to be around 50 cm(2)V(-1)s(-1). Using such devices, digital logic gates including inverters, NAND, and NOR gates with superior bending stability have been demonstrated. Moreover, radio frequency measurements show that cutoff frequency of 170 MHz can be achieved in devices with a relatively long channel length of 4 μm, which is sufficient for certain wireless communication applications. This proof-of-concept demonstration indicates that our platform can serve as a foundation for scalable, low-cost, high-performance flexible electronics.

An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers

A UWB 3.1 to 10.6 GHz LNA employing an input three-section band-pass Chebyshev filter is reported. Fabricated in a 0.18 /spl mu/m CMOS process, -10 dB over the band, a NF of 4 dB, and an IIP3 of -6.7 dBm while consuming the IC achieves a power gain of 9.3 dB with an input match of 9 mW.

Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off

This paper presents a new approach for power amplifier design using deep submicron CMOS technologies. A transformer based voltage combiner is proposed to combine power generated from several low-voltage CMOS amplifiers. Unlike other voltage combining transformers, the architecture presented in this paper provides greater flexibility to access and control the individual amplifiers in a voltage combined amplifier. In this work, this voltage combining transformer has been utilized to control output power and improve average efficiency at power back-off. This technique does not degrade instantaneous efficiency at peak power and maintains voltage gain with power back-off. A 1.2 V, 2.4 GHz fully integrated CMOS power amplifier prototype was implemented with thin-oxide transistors in a 0.13 mum RF-CMOS process to demonstrate the concept. Neither off-chip components nor bondwires are used for output matching. The power amplifier transmits 24 dBm power with 25% drain efficiency at 1 dB compression point. When driven into saturation, it transmits 27 dBm peak power with 32% drain efficiency. At power back-off, efficiency is greatly improved in the prototype which employs average efficiency enhancement circuitry.

Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuits

The Green function over a multilayer substrate is derived by solving Poissons equation analytically in the coordinate and numerically in the z and y coordinates. The x and y functional dependence is transformed into a discrete cosine transform (DCT) representation for rapid evaluation. The Green function is further transformed into a numerically stable form appropriate for finite-precision machine evaluation. This Green function is used to solve for the impedance matrix for an arbitrary three-dimensional arrangement of conductors placed anywhere in the substrate. Using this technique, the substrate coupling and loss in IC circuits can be analyzed. A spiral inductor is presented as an example. Experimental measurement results verify the accuracy of the technique.