Mukesh Agrawal

Test-cost optimization and test-flow selection for 3D-stacked ICs

Three-dimensional (3D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3D integration, test cost remains a major concern, and analysis and tools are needed to understand test flows and minimize test cost. We propose a generic cost model to account for various test costs involved in 3D integration and present a heuristic solution to minimize the overall cost. In contrast to prior work, which is based on explicit enumeration of test flows, we adopt a formal optimization approach, which allows us to select an effective test flow by systematically exploring an exponentially large number of candidate test flows. Experimental results highlight the effectiveness of the proposed heuristic solution, which is compared to an exact approach for a small test case and to a random-selection baseline method for large test cases.

Test and Design-for-Testability Solutions for 3D Integrated Circuits

Despite the promise and benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. Test techniques and design-for-testability (DfT) solutions for 3D ICs are now being studied in the research community, and experts in industry have identified a number of hard problems related to the lack of probe access for wafers, test access in stacked dies, yield enhancement, and new defects arising from unique processing steps. We describe a number of testing and DfT challenges, and present some of the solutions being advocated for these challenges. Techniques highlighted in this paper include: (i) pre-bond testing of TSVs and die logic, including probing and non-invasive test using DfT; (ii) post-bond testing and DfT innovations related to the optimization of die wrappers, test scheduling, and access to dies and inter-die interconnects; (iii) interconnect testing in interposer-based 2.5D ICs; (iv) fault diagnosis and TSV repair; (v) cost modeling and test-flow selection.

Test-Cost Modeling and Optimal Test-Flow Selection of 3-D-Stacked ICs

Three-dimensional (3-D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3-D integration, test cost remains a major concern, and analysis and tools are needed to understand test flows and minimize test cost. We propose a generic cost model to account for various test costs involved in 3-D integration and present a formal representation of the solution space to minimize the overall cost. We present an algorithm based on A*-a best-first search technique-to obtain an optimal solution. An approximation algorithm with provable bounds on optimality is proposed to further reduce the search space. In contrast to prior work, which is based on explicit enumeration of test flows, we adopt a formal optimization approach, which allows us to select an effective test flow by systematically exploring an exponentially large number of candidate test flows. Experimental results highlight the effectiveness of the proposed method. Adopting a formal approach to solving the cost-minimization problem provides useful insights that cannot be derived via selective enumeration of a smaller number of candidate test flows.

Digital print workflow optimization under due-dates, opportunity cost and resource constraints

On-demand digital printing is an example of emerging personalized manufacturing services. It provides unique opportunities to automate the printing process, enhance productivity, and better utilize resources such as equipment, servers and IT infrastructure. In this work, we present a unified solution approach to solve an important optimization problem in digital printing, viz., simultaneous mapping of component tasks of a print job to time steps (scheduling), selection of resources for these tasks, and mapping of tasks to resources (binding). We model print jobs, the relationships between them, and dependencies between tasks within a job, in terms of sequencing graphs. This formal representation is then used for scheduling and resource binding. The optimization objective is to enable justin-time manufacturing, that is, to minimize both the slack time (the duration between the delivery deadline and the completion time of the order) and the opportunity cost for job orders. The proposed approach uses genetic algorithms (GA) to systematically search the space of feasible solutions. The fitness function of the GA is carefully crafted to match the optimization objective. An integer linear programming (ILP) model is described to evaluate the GA heuristic by deriving optimal solutions for small problem instances. The optimization technique is further evaluated using print orders from a commercial print service provider and compared to baseline methods commonly implemented in the industrial settings.

Micro-Sector Cache: Improving Space Utilization in Sectored DRAM Caches

Recent research proposals on DRAM caches with conventional allocation units (64 or 128 bytes) as well as large allocation units (512 bytes to 4KB) have explored ways to minimize the space/latency impact of the tag store and maximize the effective utilization of the bandwidth. In this article, we study sectored DRAM caches that exercise large allocation units called sectors, invest reasonably small storage to maintain tag/state, enable space- and bandwidth-efficient tag/state caching due to low tag working set size and large data coverage per tag element, and minimize main memory bandwidth wastage by fetching only the useful portions of an allocated sector. However, the sectored caches suffer from poor space utilization, since a large sector is always allocated even if the sector utilization is low. The recently proposed Unison cache addresses only a special case of this problem by not allocating the sectors that have only one active block. We propose Micro-sector cache, a locality-aware sectored DRAM cache architecture that features a flexible mechanism to allocate cache blocks within a sector and a locality-aware sector replacement algorithm. Simulation studies on a set of 30 16-way multi-programmed workloads show that our proposal, when incorporated in an optimized Unison cache baseline, improves performance (weighted speedup) by 8%, 14%, and 16% on average, respectively, for 1KB, 2KB, and 4KB sectors at 128MB capacity. These performance improvements result from significantly better cache space utilization, leading to 18%, 21%, and 22% average reduction in DRAM cache read misses, respectively, for 1KB, 2KB, and 4KB sectors at 128MB capacity. We evaluate our proposal for DRAM cache capacities ranging from 128MB to 1GB.

The hype, myths, and realities of testing 3D integrated circuits

Three-dimensional (3D) integration using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moores law. Despite the promise and benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. This paper examines the hype, myths, and realities of 3D IC testing. We describe a number of testing and DfT challenges, and present some solutions being advocated for the challenges of “What to Test”, “How to Test”, and “When to Test”. Techniques highlighted in this paper include: (i) testing of the silicon interposer; (ii) pre-bond TSV testing; (iii) cost modeling and test-flow selection; (iv) a reconfigurable built-in self-test infrastructure.