Murat R. Becer

Noise propagation and failure criteria for VLSI designs

Noise analysis has become a critical concern in advanced chip designs. Traditional methods suffer from two common issues. First, noise that is propagated through the driver of a net is combined with noise injected by capacitively coupled aggressor nets using linear summation. Since this ignores the non-linear behavior of the driver gate the noise that develops on a net can be significantly underestimated. We therefore propose a new linear model that accurately combines propagated and injected noise on a net and which maintains the efficiency of linear simulation. After the propagated and injected noise are correctly combined on a victim net, it is necessary to determine if the noise can result in a functional failure. This is the second issue that we discuss in this paper. Traditionally, noise failure criteria have been based on unity gain points of the DC or AC transfer curves. However, we will show that for digital designs, these approaches can result in a pessimistic analysis in some cases, while in other cases, they allow circuit operation that is extremely close to regions that are unstable and do not allow sufficient margin for error in the analysis. In this paper, we compare the effectiveness of the discussed noise failure criteria and also present a propagation based method, which is intended to overcome these drawbacks. The proposed methods were implemented in a noise analysis tool and we demonstrate results on industrial circuits.

An analytical model for delay and crosstalk estimation with application to decoupling

The impact of interconnect coupling, in the form of delay and crosstalk, in deep submicron integrated circuit design is increasing. In many cases, especially in routing, the coupling capacitance, C/sub c/, between adjacent lines is decoupled and replaced by 2C/sub c/ connected to ground for fast worst-case delay estimation. This is based on the assumption that worst-case delay occurs when two adjacent lines switch simultaneously in opposite directions so that the voltage change across the coupling capacitance is twice that when only one line is switching. Similarly, when two adjacent lines switch simultaneously in the same direction, the coupling capacitance is put to zero based on the fact that the voltage difference across it is zero. However, we show that by replacing the coupling capacitance C/sub c/ with a grounded capacitance of 2C/sub c/ (or by zero) when signals switch simultaneously in opposite (or same) directions may overestimate or even underestimate the actual delay. The variable strengths of the drivers driving the coupled lines bring in an additional level of complexity to the delay estimation when coupling exists. In this paper, we derive a simple analytical model that takes the effect of different driver strengths into account, to accurately estimate the delay and crosstalk of two coupled interconnect lines switching simultaneously. This approach also gives the exact values of the multiplicants that C/sub c/ should be multiplied with, if the lines are to be decoupled, for both worst-case and best-case delay computation; that is when the signals switch in opposite direction and when they switch in the same direction.

Transistor level gate modeling for accurate and fast timing, noise, and power analysis

Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65 nm and below. Voltage waveform shapes are increasingly more difficult to represent as simple ramps due to highly resistive interconnects and Miller cap effects at receiver gates. Propagation of complex voltage waveforms, and accurate modeling of nonlinear driver and receiver effects in crosstalk noise analysis require accurate cell models. A good cell model should be independent of input waveform and output load, should be easy to characterize and should not increase the complexity of a cell library with high-dimensional look-up tables. At the same time, it should provide high accuracy compared to SPICE for all analysis scenarios including multiple-input switching, and for all cell types and cell arcs, including those with high stacks. It should also be easily extendable for use in statistical STA and noise analysis, and one should be able to simulate it fast enough for practical use in multi-million gate designs. In this paper, we present a gate model built from fast transistor models (FXM) that has all the desired properties. Along with this model, we also present a multithreaded timing traversal approach that allows one to take advantage of the high accuracy provided by the FXM, at traditional STA speeds. Results are presented using a fully extracted 65 nm TSMC technology.

Crosstalk noise control in an SoC physical design flow

Signal integrity closure is one of the key challenges in deep submicron physical design. In this paper, we propose a physical design methodology which includes signal integrity management through crosstalk noise analysis and repair at multiple phases of the design so that a quick noise convergence can be achieved. The methodology addresses both functional and delay noise problems in the design and is targeted for block-, platform-, and chip-level physical design of system-on-chip designs. A number of case studies are presented to illustrate the effectiveness of the proposed methodology and to provide valuable insights useful for successful signal integrity management.

SOI Transistor Model for Fast Transient Simulation

Progress in semiconductor process technology has made SOItransistors one of the most promising candidates for high performanceand low power designs. With smaller diffusion capacitances,SOI transistors switch significantly faster than theirtraditional bulk MOS counterparts and consume less power perswitching. However, design and simulation of SOI MOS circuits ismore challenging due to more complex behavior of an SOI transistorinvolving floating body effects, delay dependence on history oftransistor switching, bipolar effect and others. This paper isdevoted to developing a fast table model of SOI transistors, suitablefor use in fast transistor level simulators. We propose usingbody charge instead of body potential as an independent variableof the model to improve convergence of circuit simulation integrationalgorithm. SOI transistor has one additional terminal comparedwith the bulk MOSFET and hence requires larger tables tomodel. We propose a novel transformation to reduce number oftable dimensions and as a result to make the size of the tables reasonable.The paper also presents efficient implementation of ourSOI transistor table model using piece-wise polynomial approximation,nonuniform grid discretization, and splitting the transistormodel into the model of its equilibrium and non equilibrium states.The effectiveness of the proposed model is demonstrated byemploying it in a fast transistor level simulator to simulate highperformance industrial SOI microprocessor circuits.

Signal integrity management in an SoC physical design flow

Signal integrity closure is one of the key challenges in DSM (Deep- SubMicron) physical design. In this paper, we propose a physical design methodology which includes signal integrity management through noise analysis and repair at multiple phases of the design so that a quick noise convergence can be achieved. The methodology addresses both functional and delay noise problems in the design and is targeted for block, platform, and chip level physical design of SoC (System-On-Chip) designs. A number of case studies are presented to illustrate the effectiveness of the proposed methodology and to provide valuable insights useful for successful signal integrity management.

An analytical model for delay and crosstalk estimation in interconnects under general switching conditions

The impact of interconnect coupling, in the form of delay and crosstalk, in deep submicron integrated circuit design is increasing. In timing analysis, the delay of a critical path should include the effect of crosstalk noise due to the switching of aggressor lines. The fact that the victim and aggressor lines may or may not be switching simultaneously, and the variable strengths of the drivers driving the coupled lines bring in additional levels of complexity to the delay estimation when coupling exists. In this paper, we derive a simple analytical model that takes the effect of different driver strengths into account, to accurately estimate the delay and crosstalk of two coupled interconnect lines. The model is applicable under all switching conditions: simultaneous or nonsimultaneous; in opposite directions or in the same direction.

Early probabilistic noise estimation for capacitively coupled interconnects

One of the critical challenges in todays high performance IC design is to take noise into account as early as possible in the design cycle. Current noise analysis tools [1, 7} are effective at analyzing and identifying noise in the post-route design stage when detailed parasitic information is available. However, noise problems identified at this stage of design cycle are very difficult to fix due to the limited flexibility in the design and may cause additional iterations of routing and placement, adding costly delays to time-to-market. In this paper, we introduce an estimated, congestion-based pre-route noise analysis approach to identify post-route noise failures before the actual detailed route is completed. We introduce new methods to estimate the RC characteristics of victim and aggressor lines, their coupling capacitances and the aggressor transition times before routing is performed. The approach is based on congestion information obtained from a global router. Since the exact location and relative position of wires in the design is not yet available at this point, we propose a novel probabilistic method for capacitance extraction. We present results on two high performance microprocessors in 0.18μ technology that demonstate the effectiveness of the proposed approac.

A global driver sizing tool for functional crosstalk noise avoidance

As coupling noise analysis and estimation is reaching a relative maturity with recent efforts, more effort is needed in correcting and/or avoiding failures that can be caused by coupling noise. In this paper, we present a global driver sizing tool which can be used in a complete noise avoidance tool along with other techniques such as wire spacing and wire sizing. The proposed approach is used along with ClariNet, which is a recent noise analysis tool, in a greater effort towards a total signal integrity solution. We first present the analytical, linear interconnect model used. We then show how this model is used to provide necessary information for global driver sizing along with our novel algorithm. We finally present results on two industrial circuits including a large high performance control block.

Static electromigration analysis for signal interconnects

With the increase in current densities, electromigration has become a critical concern in high-performance designs. Typically, electromigration has involved the process of time-domain simulation of drivers and interconnect to obtain average, RMS, and peak current values for each wire segment. However, this approach cannot be applied to large problem sizes where hundreds of thousands of nets must be analyzed, each consisting of many thousands of RC elements. In this paper, we propose a static electromigration analysis approach. We show that under conditions that are typically met by VLSI interconnects, the charge transfer through wire segments of a net can be calculated directly by solving a system of linear equations, thereby eliminating the need for time domain simulation. Also, we prove that under these conditions the charge transfer through a wire segment is independent of the shape of the driver current waveform. From the charge transfer through each wire segment, the average current is obtained directly, as well as approximate RMS and peak currents. We account for the different possible switching scenarios that give rise to unidirectional or bi-directional current by separating the charge transfer from the rising and falling transitions, and also propose approaches for modeling multiple simultaneous switching drivers. The results on a number of industrial circuits demonstrate the accuracy and efficiency of the approach.