Alexey Glebov

Library-less synthesis for static CMOS combinational logic circuits

Traditional synthesis techniques optimize CMOS circuits in two phases: i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield good synthesis results over many blocks or even for an entire chip. Consequently this approach precludes an optimal design of individual blocks which may need custom structures. The authors present a new transistor level technique that optimizes CMOS circuits both structurally and size-wise. The technique is independent of a library and hence can explore a design space much larger than that possible due to gate level optimization. Results demonstrate a significant improvement in circuit performance of the resynthesized circuits.

False-noise analysis using resolution method

High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use the conservative assumption that all neighbors of a net can switch simultaneously, thereby producing the worst-case noise on a net. However, due to the logic correlations in the circuit, this worst-case noise may not be realizable, resulting in a so-called false noise failure. Since the problem has been shown to be NP-hard in general, exact solutions to this problem are not possible. In this paper, we therefore propose a new heuristic to eliminate false noise failures based on the resolution method. It is shown that multi-variable logic relations can be computed directly from a transistor level description. Based on these generated logic relations, a characteristic ROBDD for a signal net and its neighboring nets is constructed. This ROBDD is then used to determine the set of neighboring nets that result in the maximum realizable noise on the net. The proposed approach was implemented and tested on industrial circuits. The results demonstrate the effectiveness of the approach to eliminate false noise failures.

Delay noise pessimism reduction by logic correlations

High-performance digital circuits are facing increasingly severe signal integrity problems due to crosstalk noise and therefore the state-of-the-art static timing analysis (STA) methods consider crosstalk-induced delay variation. Current noise-aware STA methods compute noise-induced delay uncertainty for each net independently and annotate appropriate delay changes of nets onto data paths and associated clock paths to determine timing violations. Since delay changes in individual nets contribute cumulatively to delay changes of paths, even small amounts of pessimism in noise computation of nets can add up to produce large timing violations for paths, which may be unrealistic. Unlike glitch noise analysis where noise often attenuates during propagation, quality of delay noise analysis is severely affected by any pessimism in noise estimation and can unnecessarily cost valuable silicon and design resources for fixing unreal violations. In this paper, we propose a method to reduce pessimism in noise-aware STA by considering signal correlations of all nets associated with an entire timing path simultaneously, in a path-based approach. We first present an exact algorithm based on the branch-and-bound technique and then extend it with several heuristic techniques so that very large industrial designs can be analyzed efficiently. These techniques, which are implemented in an industrial crosstalk noise analysis tool, show as much as 75% reduction in the computed path delay variations.

Calculation of stress probability for NBTI-aware timing analysis

Negative bias temperature instability (NBTI) has become a primary mechanism that degrades performance of integrated circuits. It is well known that NBTI impacts pMOS transistors during circuit operation, and the degradation occurs when pMOS transistor is in a conducting state. So, accurate NBTI degradation analysis requires analysis of logic states. Degradation of specific pMOS transistor depends on part of lifetime, in which this transistor is under stress, in other words, on stress probability. In this paper, we propose the correct algorithm of calculating stress probability for every pMOS transistor of complex CMOS gate. Comparing to simple ¿naive¿ approach, our algorithm takes into account two additional factors: correlations between signals at gate inputs, and VDD-potential coming through ¿bottom¿ of pMOS transistor. Numerical experiments show the importance of accounting for both these factors.

SOI Transistor Model for Fast Transient Simulation

Progress in semiconductor process technology has made SOItransistors one of the most promising candidates for high performanceand low power designs. With smaller diffusion capacitances,SOI transistors switch significantly faster than theirtraditional bulk MOS counterparts and consume less power perswitching. However, design and simulation of SOI MOS circuits ismore challenging due to more complex behavior of an SOI transistorinvolving floating body effects, delay dependence on history oftransistor switching, bipolar effect and others. This paper isdevoted to developing a fast table model of SOI transistors, suitablefor use in fast transistor level simulators. We propose usingbody charge instead of body potential as an independent variableof the model to improve convergence of circuit simulation integrationalgorithm. SOI transistor has one additional terminal comparedwith the bulk MOSFET and hence requires larger tables tomodel. We propose a novel transformation to reduce number oftable dimensions and as a result to make the size of the tables reasonable.The paper also presents efficient implementation of ourSOI transistor table model using piece-wise polynomial approximation,nonuniform grid discretization, and splitting the transistormodel into the model of its equilibrium and non equilibrium states.The effectiveness of the proposed model is demonstrated byemploying it in a fast transistor level simulator to simulate highperformance industrial SOI microprocessor circuits.

False-noise analysis using logic implications

Cross-coupled noise analysis has become a critical concern in todays VLSI designs. Typically, noise analysis makes the assumption that all aggressing nets can simultaneously switch in the same direction. This creates a worst- case noise pulse on the victim net that often leads to false noise violations. In this article we present a new approach that uses logic implications to identify the maximum set of aggressor nets that can inject noise simultaneously under the logic constraints of the circuit. We propose an approach to efficiently generate logic implications from a transistor-level description and propagate them in the circuit using ROBDD representations. We propose a new method for lateral propagation of implications and also show how tristate gates and high-impedance signal states can be handled using tristate implications. We then show that the problem of finding the worst-case logically feasible noise can be represented as a maximum weighted independent set problem and show how to efficiently solve it. Initially, we restrict our discussion to zero-delay implications, which are valid for glitch-free circuits, and then extend our approach to timed implications. The proposed approaches were implemented in an industrial noise analysis tool and results are shown for a number of industrial test cases. We demonstrate that a significant reduction in the number of noise failures can be obtained from considering the logic implications as proposed in this article, underscoring the need for false-noise analysis.Crosstalk noise becomes one of the critical issues gating design closure for nano-meter designs. Pessimism in noise analysis can lead to significant additional time spent addressing false violations. Taking logic correlation into consideration, noise analysis can reduce pessimism significantly by eliminating false noise signals [1]-[3][5]-[7][10]-[13]. Eliminating the aggressors from the aggressor candidate set that can not switch simultaneously restricted by the logic exclusivity (LE) relationship among them can save simulation time as well. The LE problem, being proved as NP-complete, is basically to determine the subset (possibly multiple equivalent subsets) of a given aggressor candidate set which has the largest combined weight out of all possible subsets governed by logic exclusivity constraints. This paper presents a new approach in resolving the LE problem, which employs a gain guided backtrack search technique that does not require exhaustive search of all the binary paths to reach an optimal solution. We first prove that under certain conditions, if the gain at each level is non-negative, then the result will be optimal. Based on this theorem, a new algorithm is developed. The experimental results demonstrate the efficiency and accuracy of this approach. The algorithm can quickly find the optimal solutions for most cases from industry designs and outperforms other methods.

False-noise analysis for domino circuits

High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use the conservative assumption that all neighbors of a net can switch simultaneously, producing the worst-case noise. However, due to logic correlations in the circuit, this worst-case noise may not be realizable, resulting in a so-called false noise failure. Some techniques for computing logic correlations have been designed targeting static CMOS circuits. However high performance microprocessors commonly use domino logic for their ALU. The domino circuits have lower noise margins than static CMOS circuits and are more sensitive to coupled noise. Any unnecessary pessimism of the noise analysis tool results in large number of false noise violations and either requires additional extensive SPICE simulations or circuit over-design. Unfortunately false noise analysis developed for static CMOS circuits fails to compute many logic correlations in domino circuits. In this paper we propose a novel technique of computing logic correlations in domino circuits. It takes into account the fact that both pull up and pull down networks of a domino gate can be in non conducting state. The proposed technique generates additional logic correlations for such states of domino gates. In order to improve the capability of logic correlation derivation technique we combine the resolution method with recursive learning algorithm. The proposed technique is implemented in an industrial noise analysis tool and tested on high performance ALU blocks.