Muzammil Iqbal

Multiscale free-space optical interconnects for intrachip global communication: motivation, analysis, and experimental validation.

The use of optical interconnects for communication between points on a microchip is motivated by system-level interconnect modeling showing the saturation of metal wire capacity at the global layer. Free-space optical solutions are analyzed for intrachip communication at the global layer. A multiscale solution comprising microlenses, etched compound slope microprisms, and a curved mirror is shown to outperform a single-scale alternative. Microprisms are designed and fabricated and inserted into an optical setup apparatus to experimentally validate the concept. The multiscale free-space system is shown to have the potential to provide the bandwidth density and configuration flexibility required for global communication in future generations of microchips.

Stochastic wire length sampling for cycle time estimation

Cycle time models perform an a-priori calculation of local signal delays by estimating the lengths of wires connecting different levels of synchronously clocked logic elements. Typically, a signal will have to pass through approximately 15-25 layers of logic during a single clock cycle and it is has been assumed that this number is sufficiently large to allow average wire lengths to be used. This paper investigates the accuracy of this mean value assumption by comparing cycle times calculating using average wire lengths with cycle times calculated using wires sampled from an estimate of the wire length distribution in each wiring layer. The sampling algorithm provides a more accurate calculation of the cycle time and also an estimate of its variation due to the inherently stochastic nature of the layout process. Results for a benchmark netlist, implemented in 0.25 μm technology, indicate that for a logic depth of 25 the mean value assumption is satisfactory and that clock rate has a standard deviation of approximately 5% of this mean value due to the inherently stochastic nature of the layout process.

Multiscale free-space optical interconnects for intrachip global communications

Optical intrachip global interconnects are discussed. Methods for replacing metal global interconnects with free-space optical interconnects are compared analytically to highlight the bandwidth capacity benefits of using a multiscale optical system for intrachip global communications.

Optical interconnects for intrachip global communication: motivation & validation

Optical interconnects have the potential to prevent the performance saturation due to the limitations of global wires in future microchips. Global communication issues are analyzed and potential optical interconnect-based solutions are motivated and validated.

Coupling Structure for Intrachip Optical Global Communication: Design and Simulation

Hybrid optical interconnects are a potential solution to the density, latency and power consumption issues of on-chip global wires. Simulations and analysis of an efficient coupling scheme for a MQW modulator-based waveguide fabric are presented

Arbitrarily Configurable Optical Interconnect Fabric for Intrachip Global Communication

Optical interconnections at the chip level may provide solutions to the limitations of metal interconnect technology, which is not keeping pace with the progress of device integration density. In this paper we undertake a quantitative analysis of on-chip metal interconnect performance as CMOS device technology scales into the nanometer regime. The results of this analysis motivates the use of optical interconnects as a replacement for global wires on the chip. We propose a new architecture, in which a 3-D optoelectronic Application Specific Interconnection Fabric (ASIF) is coupled to a conventional Silicon integrated circuit to alleviate the performance-limiting aspects of long metal interconnects. The overall goal of the ASIF concept is to overcome the limitations of conventional metal interconnects in a manner that can be seamlessly integrated according to current VLSI design constraints and practices.Copyright

Experimental Validation of a Multi-scale Free-space Intra-chip Optical Interconnection Fabric Concept

In this paper, key aspects of a 3-D optoelectronic application specific interconnection fabric system are demonstrated. The approach uses an array of high-density, precisely oriented micro-prisms that are lithographically fabricated to affect an arbitrary global interconnection fabric

Progress toward optical interconnects for intrachip global communication

Microprocessor performance is now limited by the poor delay and bandwidth performance of the on-chip global wiring layers. Although relatively few in number, the global metal wires have proven to be the primary cause of performance limitations - effectively leading to a premature saturation of Moores Law scaling in future Silicon generations. Building upon device-, circuit-, system- and architectural-level models, a framework for performance evaluation of global wires is developed aimed at quantifying the major challenges faced by intrachip global communications over the span of six technology generations. This paper reviews the status of possible intra-chip optical interconnect solutions in which the Silicon chips global metal wiring layers are replaced with a high-density guided-wave or free-space optical interconnection fabric. The overall goal is to provide a scalable approach that is compatible with established silicon chip fabrication and packaging technology, and which can extend the reach of Moores Law for many generations to come. To achieve the required densities, the integrated sources are envisioned to be modulators that are optically powered by off-chip sources. Structures for coupling dense modulator arrays to optical power sources and to free-space or guide-wave optical global fabrics are analyzed. Results of proof-of-concept experiments, which demonstrate the potential benefits of ultra-high-density optical interconnection fabrics for intra-chip global communications, are presented.

System-level performance estimation of an optoelectronic Viterbi decoder

The Optoelectronic Viterbi Decoder (OVD) in [1] is proposed to alleviate the interconnect bottleneck prevalent in high speed, fully parallel, multi-chip Viterbi decoders used in digital communication systems to decode long constraint length convolutional codes. The OVD utilizes a reflective optical system comprised of a macro-lens array and a mirror to globally interconnect VCSEL/MSM PD based smart pixel arrays distributed across multiple OEIC’s on a PCB or MCM. Smart pixels that possess identical functionality are clustered on the chips and interconnected with VLSI interconnects. This hybrid approach of optical/electrical interconnects overcomes the interconnect density and speed limitations of traditional VLSI approaches to long constraint length decoding and provides high decoder throughput and trace-back speed by maintaining on-chip speeds between chips. This paper presents a model for the OEIC’s of the OVD, and estimates decoder speed by utilizing interconnect prediction [2] and stochastic cycle time models [3].