Michael J. McFadden

Multiscale free-space optical interconnects for intrachip global communication: motivation, analysis, and experimental validation.

The use of optical interconnects for communication between points on a microchip is motivated by system-level interconnect modeling showing the saturation of metal wire capacity at the global layer. Free-space optical solutions are analyzed for intrachip communication at the global layer. A multiscale solution comprising microlenses, etched compound slope microprisms, and a curved mirror is shown to outperform a single-scale alternative. Microprisms are designed and fabricated and inserted into an optical setup apparatus to experimentally validate the concept. The multiscale free-space system is shown to have the potential to provide the bandwidth density and configuration flexibility required for global communication in future generations of microchips.

ACTIVE-EYES: an adaptive pixel-by-pixel image-segmentation sensor architecture for high-dynamic-range hyperspectral imaging

The ACTIVE-EYES (adaptive control for thermal imagers via electro-optic elements to yield an enhanced sensor) architecture, an adaptive image-segmentation and processing architecture, based on digital micromirror (DMD) array technology, is described. The concept provides efficient front-end processing of multispectral image data by adaptively segmenting and routing portions of the scene data concurrently to an imager and a spectrometer. The goal is to provide a large reduction in the amount of data required to be sensed in a multispectral imager by means of preprocessing the data to extract the most useful spatial and spectral information during detection. The DMD array provides the flexibility to perform a wide range of spatial and spectral analyses on the scene data. The spatial and spectral processing for different portions of the input scene can be tailored in real time to achieve a variety of preprocessing functions. Since the detected intensity of individual pixels may be controlled, the spatial image can be analyzed with gain varied on a pixel-by-pixel basis to enhance dynamic range. Coarse or fine spectral resolution can be achieved in the spectrometer by use of dynamically controllable or addressable dispersion elements. An experimental prototype, which demonstrated the segmentation between an imager and a grating spectrometer, was demonstrated and shown to achieve programmable pixelated intensity control. An information theoretic analysis of the dynamic-range control aspect was conducted to predict the performance enhancements that might be achieved with this architecture. The results indicate that, with a properly configured algorithm, the concept achieves the greatest relative information recovery from a detected image when the scene is made up of a relatively large area of moderate-dynamic-range pixels and a relatively smaller area of strong pixels that would tend to saturate a conventional sensor.

A 2-Gb/s 0.5-/spl mu/m CMOS parallel optical transceiver with fast power-on capability

This paper describes an optical transceiver designed for power-efficient connections within high-speed digital systems, specifically for board- and backplane-level interconnections. A 2-Gb/s, four-channel, dc-coupled differential optical transceiver was fabricated in a 0.5-/spl mu/m complementary metal-oxide-semiconductor (CMOS) silicon-on-sapphire (SoS) process and incorporates fast individual-channel power-down and power-on functions. A dynamic sleep transistor technique is used to turn off transceiver circuits and optical devices during power-down. Differential signaling (using two optical channels per signal) enables self-thresholding and allows the transceiver to quickly return from power-down to normal operation. A free-space optical link system was built to evaluate transceiver performance. Experimental results show power-down and power-on transition times to be within a few nanoseconds. Crosstalk measurements show that these transitions do not significantly impact signal integrity of adjacent active channels.

Multiscale free-space optical interconnects for intrachip global communications

Optical intrachip global interconnects are discussed. Methods for replacing metal global interconnects with free-space optical interconnects are compared analytically to highlight the bandwidth capacity benefits of using a multiscale optical system for intrachip global communications.

Optical interconnects for intrachip global communication: motivation & validation

Optical interconnects have the potential to prevent the performance saturation due to the limitations of global wires in future microchips. Global communication issues are analyzed and potential optical interconnect-based solutions are motivated and validated.

Performance-based adaptive power optimization for digital optical interconnects

Optical links are traditionally set to transmit maximum power for worst-case loss and consequently to dissipate more power than is required. We describe a technique to minimize power consumption based on the measured bit-error rate (BER) of the link. This technique uses a novel power-negotiation algorithm that optimizes the link power setting to achieve minimum power dissipation for a target BER. A 0.5 microm complementary metal-oxide semiconductor optical transceiver chip was fabricated, and a free-space optical interconnect system was built for validation. The results showed that the algorithm was able to find the optimum power settings for the VCSELs for a target BER and to account for dynamic changes such as variation in the optical loss in the system.

Experimental validation of hybrid micro-macro optical method for distortion removal in multi-chip global free-space optical-interconnection systems

Experimental validation of a distortion removal technique for multi-chip free-space optical shuffle interconnections is presented. The free-space fabric links dense two-dimensional arrays of vertical cavity surface emitting laser(s) (VCSEL)(s) and detectors and must achieve full field registration on the order of 10 microns across the entire array. The new hybrid micro-macro optical concept realizes the required high-registration accuracy by simultaneously eliminating distortion in each of the interleaved off-axis imaging systems that comprise the complete fabric. This is achieved by exploiting the typically low numerical aperture of VCSELs. Individually tailored beam-deflecting micro-optical elements were used to create symmetry about a central aperture for VCSEL beams in the optical system. Experiments were developed to quantify the registration accuracy, the VCSEL images, and the associated spot sizes. The experimental results show that beam steering can be implemented to remove distortion in off-axis free-space optical-interconnection systems.

Power-efficient dual-rate optical transceiver

A dual-rate (2 Gbit/s and 100 Mbit/s) optical transceiver designed for power-efficient connections within and between modern high-speed digital systems is described. The transceiver can dynamically adjust its data rate according to performance requirements, allowing for power-on-demand operation. Dynamic power management permits energy saving and lowers device operating temperatures, improving the reliability and lifetime of optoelectronic-devices such as vertical-cavity surface-emitting lasers (VCSELs). To implement dual-rate functionality, we include in the transmitter and receiver circuits separate high-speed and low-power data path modules. The high-speed module is designed for gigabit operation to achieve high bandwidth. A simpler low-power module is designed for megabit data transmission with low power consumption. The transceiver is fabricated in a 0.5 microm silicon-on-sapphire complementary metal-oxide semiconductor. The VCSEL and photodetector devices are attached to the transceivers integrated circuit by flip-chip bonding. A free-space optical link system is constructed to demonstrate correct dual-rate functionality. Experimental results show reliable link operation at 2 Gbit/s and 100 Mbit/s data transfer rates with approximately 104 and approximately 9 mW power consumption, respectively. The transceivers switching time between these two data rates is demonstrated as 10 micros, which is limited by on-chip register reconfiguration time. Improvement of this switching time can be obtained by use of dedicated input-output pads for dual-rate control signals.

Arbitrarily Configurable Optical Interconnect Fabric for Intrachip Global Communication

Optical interconnections at the chip level may provide solutions to the limitations of metal interconnect technology, which is not keeping pace with the progress of device integration density. In this paper we undertake a quantitative analysis of on-chip metal interconnect performance as CMOS device technology scales into the nanometer regime. The results of this analysis motivates the use of optical interconnects as a replacement for global wires on the chip. We propose a new architecture, in which a 3-D optoelectronic Application Specific Interconnection Fabric (ASIF) is coupled to a conventional Silicon integrated circuit to alleviate the performance-limiting aspects of long metal interconnects. The overall goal of the ASIF concept is to overcome the limitations of conventional metal interconnects in a manner that can be seamlessly integrated according to current VLSI design constraints and practices.Copyright

Source Synchronous Double Data Rate (DDR) Parallel Optical Interconnects

Double data rate (DDR) signaling is widely used in electrical interconnects to eliminate clock recovery and to double communication bandwidth. This paper describes the design of a parallel optical transceiver integrated circuit (IC) that uses source-synchronous, DDR optical signaling. On the transmit side, two 8-bit electrical inputs are multiplexed, encoded and sent over two high-speed optical links. On the receive side, the procedure is reversed to produce two 8-bit electrical outputs. Our IC integrates analog Vertical Cavity Surface Emitting Lasers (VCSEL), drivers and optical receivers with digital DDR multiplexing, serialization, and deserializaton circuits. It was fabricated in a 0.5-micron Silicon-on-Sapphire (SOS) CMOS process. Linear arrays of quad VCSELs and photodetectors were attached to our transceiver IC using flip-chip bonding. A free-space optical link system was constructed to demonstrate correct IC functionality. The test results show successful transceiver operation at a data rate of 500 Mbps with a 250 MHz DDR clock, achieving a gigabit of aggregate bandwidth. While our DDR scheme is well suited for low-skew fiber-ribbon, free-space and waveguide optical links, it can also be extended to links with higher skew with the addition of skew-compensation circuitry. To our knowledge, this is the first demonstration of parallel optical transceivers that use source-synchronous DDR signaling.Copyright