Myoung-Su Yang

Coplanar amorphous-indium-gallium-zinc-oxide thin film transistor with He plasma treated heavily doped layer

We report thermally stable coplanar amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with heavily doped n+ a-IGZO source/drain regions. Doping is through He plasma treatment in which the resistivity of the a-IGZO decreases from 2.98 Ω cm to 2.79 × 10−3 Ω cm after treatment, and then it increases to 7.92 × 10−2 Ω cm after annealing at 300 °C. From the analysis of X-ray photoelectron spectroscopy, the concentration of oxygen vacancies in He plasma treated n+a-IGZO does not change much after thermal annealing at 300 °C, indicating thermally stable n+ a-IGZO, even for TFTs with channel length L = 4 μm. Field-effect mobility of the coplanar a-IGZO TFTs with He plasma treatment changes from 10.7 to 9.2 cm2/V s after annealing at 300 °C, but the performance of the a-IGZO TFT with Ar or H2 plasma treatment degrades significantly after 300 °C annealing.

25.4L: Late‐News Paper: A Novel Polarizer Glasses‐Type 3D Displays with an Active Retarder

In this paper, we suggested a novel method achieving high resolution and high brightness in the glasses-type 3D displays and fabricated a prototype of 15″ size in diagonal, which is composed of an active retarder synchronized with an image panel. The active retarder is configured to a TN mode to have a function of polarization switching for the input polarization states. We expect that the AR3D technology can give high resolution and high brightness for the 3D users with a convenience of simple polarizer glasses and an inexpensive cost compared with the shutter glasses type 3D display, where not only the image panel and but also the glasses should have an LCD panel.

A Novel Five-Photomask Low-Temperature Polycrystalline Silicon CMOS Structure for AMLCD Application

A novel five-mask low-temperature polycrystalline silicon (LTPS) CMOS structure was verified by manufacturing the thin-film transistor test samples using the proposed five-mask LTPS CMOS process. In integrating the five-mask CMOS structure, a selective contact barrier metal formation process was developed, without additional photomask steps, to solve the issue of high-contact-resistance problem encountered inevitably in the contact between the indium tin oxide and doped polycrystalline silicon (poly-Si) source-drain layers. The five-mask CMOS technology was also confirmed by manufacturing a five-mask CMOS panel for the active-matrix liquid-crystal-display application.

A novel five-photo-mask low-temperature polycrystalline-silicon CMOS structure

A novel five-mask low temperature polycrystalline silicon (LTPS) complementary metal oxide semiconductor (CMOS) structure was verified by manufacturing Thin Film Transistor (TFT) test samples using the proposed five-mask LTPS CMOS process. In integrating the five-mask CMOS structure, a selective contact barrier metal formation process was developed without additional photo mask steps to solve the issue of high contact resistance problem encountered inevitably in the contact between indium tin oxide ITO and doped poly-Si source/drain layers. The five-mask CMOS technology was also confirmed by manufacturing a five-mask CMOS panel to be acceptable for the active matrix liquid crystal display (AMLCD) application.

Characteristics of IGZO Films Formed by Room Temperature with Thermal Annealing Temperature.

We investigated the structural, electrical and optical characteristics of IGZO thin films deposited by a roomtemperature RF reactive magnetron sputtering. The thin films deposited were annealed for 2 hours at various temperatures of 300, 400, 500 and 600 o C and analyzed by using X-ray diffractometer, transmission electron microscopy, atomic force microscope and Hall effects measurement system. The films annealed at 600 o C were found to be crystallized and their surface roughness was decreased from 0.73 nm to 0.67 nm. According to XPS measurements, concentration of oxygen vacancies were decreased at 600 o C. Optical band gap were increased to 3.31eV. The carrier concentration and Hall mobility were sharply increased at 600 o C. Our results indicate that the IGZO films deposited at a room temperature can show better thin film properties through a heat treatment.

Electrical characterization of polycrystalline silicon thin film transistors crystallized by a new alignment sequential lateral solidification process

In the conventional sequential lateral solidification (SLS) method for polycrystalline silicon thin-film transistors (poly-Si TFTs), as a starting process in general, one just performs a basic pre-alignment of the substrate on the stage and applies laser irradiation for a whole substrate area scan. Therefore, each thin-film transistor (TFT) has different grain boundary (GB) locations in a corresponding channel region. The number of GBs in the channel also varies from one to two, which can give rise to electrically non-uniform TFT characteristics and an image quality deterioration of the panel. We developed a new alignment SLS method for controlling the GB location in the TFT channel region, allowing us to locate the GB at the same position in the channel region of each TFT. We fabricated TFT by applying the new alignment SLS process and compared the TFT electrical characteristics between a normal SLS method and the new one. We also analyzed degradation phenomena under hot carrier stress conditions for lightly doped drain n-type metal oxide semiconducting field effect transistors.

17.2: A Novel Five‐PhotoMask LTPS CMOS Structure with Improved Storage Capacitor for AMLCD Application

A novel fivemask low temperature polycrystalline silicon LTPS complementary metal oxide semiconductor CMOS structure was verified by manufacturing the thin film transistor TFT test samples using the proposed fivemask LTPS CMOS process. In integrating the fivemask CMOS structure, a selective storage area formation process was developed, without additional photo mask steps, to solve the sputtering damage encountered inevitably in the contact between polycrystalline silicon pSi and storage metal. In addition, the selectively thin dielectric layer increased capacitance per unit area, and thus, increased the aperture ratio of AMLCD panel by reducing the capacitor area without reducing GI thickness in TFT

6.1: A Study of the Relationship Between the Image Quality of the LCD and the Nano‐Scaled Bumps on the Substrate Glass

As the mother glass size is increased and the high image quality is required, the relationship between the image quality and the glass surface becomes significant more and more. The nano-scaled bump of the glass, so called a cord, a streak, and a thickness band is one of the main factors in the image quality. The LCD panel with the nano-scaled bumps on the glass was fabricated and studied their effect on the image quality. In this paper, we introduced the mechanism for the degradation of the image quality caused by the relationship between the LCDs structure and the lens effect by the bump of the glass.