Kum-Mi Oh

A Novel Five-Photomask Low-Temperature Polycrystalline Silicon CMOS Structure for AMLCD Application

A novel five-mask low-temperature polycrystalline silicon (LTPS) CMOS structure was verified by manufacturing the thin-film transistor test samples using the proposed five-mask LTPS CMOS process. In integrating the five-mask CMOS structure, a selective contact barrier metal formation process was developed, without additional photomask steps, to solve the issue of high-contact-resistance problem encountered inevitably in the contact between the indium tin oxide and doped polycrystalline silicon (poly-Si) source-drain layers. The five-mask CMOS technology was also confirmed by manufacturing a five-mask CMOS panel for the active-matrix liquid-crystal-display application.

A novel five-photo-mask low-temperature polycrystalline-silicon CMOS structure

A novel five-mask low temperature polycrystalline silicon (LTPS) complementary metal oxide semiconductor (CMOS) structure was verified by manufacturing Thin Film Transistor (TFT) test samples using the proposed five-mask LTPS CMOS process. In integrating the five-mask CMOS structure, a selective contact barrier metal formation process was developed without additional photo mask steps to solve the issue of high contact resistance problem encountered inevitably in the contact between indium tin oxide ITO and doped poly-Si source/drain layers. The five-mask CMOS technology was also confirmed by manufacturing a five-mask CMOS panel to be acceptable for the active matrix liquid crystal display (AMLCD) application.

Electrical Characteristics of Low-Temperature Polycrystalline Silicon Complementary Metal–Oxide–Semiconductor Thin-Film Transistors with Six-Step Photomask Structure

We propose two types of six-step photomask, complementary metal–oxide–semiconductor (CMOS), thin-film transistor (TFT) PCT device structures in order to simplify their fabrication process compared with that of conventional, low-temperature, polycrystalline silicon (LTPS) CMOS TFT devices. The initial charge transfer characteristics of both types of six-step PCT are equivalent to those of the conventional nine-step PCT. Both types of six-step PCT are comparable to the conventional nine-step mask lightly doped drain (LDD) device in terms of the dc device lifetime of over 10 years at Vds=5 V for line inversion driving, which is the normally recognized duration time for semiconducting devices.

17.2: A Novel Five‐PhotoMask LTPS CMOS Structure with Improved Storage Capacitor for AMLCD Application

A novel fivemask low temperature polycrystalline silicon LTPS complementary metal oxide semiconductor CMOS structure was verified by manufacturing the thin film transistor TFT test samples using the proposed fivemask LTPS CMOS process. In integrating the fivemask CMOS structure, a selective storage area formation process was developed, without additional photo mask steps, to solve the sputtering damage encountered inevitably in the contact between polycrystalline silicon pSi and storage metal. In addition, the selectively thin dielectric layer increased capacitance per unit area, and thus, increased the aperture ratio of AMLCD panel by reducing the capacitor area without reducing GI thickness in TFT

6.1: A Study of the Relationship Between the Image Quality of the LCD and the Nano‐Scaled Bumps on the Substrate Glass

As the mother glass size is increased and the high image quality is required, the relationship between the image quality and the glass surface becomes significant more and more. The nano-scaled bump of the glass, so called a cord, a streak, and a thickness band is one of the main factors in the image quality. The LCD panel with the nano-scaled bumps on the glass was fabricated and studied their effect on the image quality. In this paper, we introduced the mechanism for the degradation of the image quality caused by the relationship between the LCDs structure and the lens effect by the bump of the glass.