N. Basanta Singh

Work Function Engineering With Linearly Graded Binary Metal Alloy Gate Electrode for Short-Channel SOI MOSFET

Over the last few decades, silicon-on-insulator (SOI) technology has been identified as one possible solution for enhancing the performance of CMOS because of its numerous advantages over conventional bulk CMOS technology. One of the primary drawbacks of short-channel SOI MOSFET is the degradation of device threshold voltage with decreasing channel length. Drain-induced barrier-lowering (DIBL) effect, generated from high drain bias, is the main cause behind this length-dependent nature of threshold voltage. This “instability” in threshold voltage is responsible for making SOI device design very challenging. The instability that is known as the threshold voltage rolloff restricts further scaling of SOI devices. In this paper, an idea of work function engineering with continuous horizontal mole fraction variation in a binary alloy gate has been proposed and implemented theoretically. Analytical model-based simulation verified that performance of proposed SOI MOSFET is improved as it has higher immunity to DIBL effect.

Design and simulation of hybrid CMOS–SET circuits

Abstract Single electron devices have extremely poor driving capabilities so that direct application to practical circuits is as yet almost impossible. A new methodology to overcome this problem is to build hybrid circuits consisting of single electron transistors (SETs) and CMOS interfaces. In this work a room temperature operable hybrid CMOS–SET inverter circuit, hybrid CMOS–SET NOR gate and their Voltage Transfer Characteristics (VTCs) are proposed. The MIB compact model for SET device and BSIM4.6.1 model for CMOS are used. The operation of the proposed circuit is verified in Tanner environment. Based on the hybrid CMOS–SET inverter, other logic gates such as NAND, NOR, AND, OR, XOR and XNOR are proposed. All the circuits are verified by means of T-Spice simulation software.

A two-dimensional analytical-model-based comparative threshold performance analysis of SOI-SON MOSFETs

A generalized threshold voltage model based on two-dimensional Poisson analysis has been developed for SOI/SON MOSFETs. Different short channel field effects, such as fringing fields, junction-induced lateral fields and substrate fields, are carefully investigated, and the related drain-induced barrier-lowering effects are incorporated in the analytical threshold voltage model. Through analytical model-based simulation, the threshold voltage roll-off and subthreshold slope for both structures are compared for different operational and structural parameter variations. Results of analytical simulation are compared with the results of the ATLAS 2D physics-based simulator for verification of the analytical model. The performance of an SON MOSFET is found to be significantly different from a conventional SOI MOSFET. The short channel effects are found to be reduced in an SON, thereby resulting in a lower threshold voltage roll-off and a smaller subthreshold slope. This type of analysis is quite useful to figure out the performance improvement of SON over SOI structures for next generation short channel MOS devices.

Analytical I–V model of SOI and SON MOSFETs: a comparative analysis

A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement.

Particle swarm approach for parameter optimization of quantum well nano structure

Analytical optimization techniques suffer from slow convergence in complex solution space. Heuristics-based swarm intelligence is an efficient alternative to analytical optimization techniques. In this paper, particle swarm optimization approach is utilized for better and efficient nano-device modeling. Mobility of two-dimensional hot electrons in modulation doped square quantum well of AlGaAs/GaAs which is determined using heated drifted Fermi-Dirac distribution function and relevant scattering mechanisms is taken as the fitness/objective function. The 2D carrier concentration, quantum well width and lattice temperature of the quantum well are taken as the input variables. The algorithm with three input variables is then utilized to get optimized values of input parameters to get desired ac and dc mobility values.

Implementation Aspects of Logic Functions using Single Electron Threshold Logic Gates and Hybrid SET-MOS Circuits

ABSTRACT Single electron technology is an attractive technology for future low-power VLSI/ULSI systems. Single electronics implies the possibility to control the movement and position of a single electron or a small amount of electrons. In this work, design, implementation, and analysis of logic functions are presented using single electron threshold logic gate (TLG) and hybrid SET-MOS circuits. The logic operation of the designed circuit is tested using Monte Carlo-based simulation tool SIMON for the single electron threshold logic circuit. For the hybrid SET-MOS-based implementation, the logic operation of the circuit is verified in Tanner environment. A compact analytical model with 11 island states for SET devices and BSIM4.6.1 model for MOS is used. The influence of thermal fluctuation on the stability of the threshold logic-based circuit, caused by increase in system temperature, has been thoroughly investigated. The effect of island states on the performance of the hybrid SET-MOS circuit is analysed. Finally, the performances of both the design approaches have been analysed and compared in terms of circuit elements, voltage levels, power consumption, and delay.

Design and implementation of an asynchronous arbiter circuit using SET CMOS hybrid architecture approach

This paper demonstrates a CMOS Single electron transistor (SET) hybrid arbiter circuit which will act like a communication switch between multiple resources. The proposed architecture combines the merits of CMOS and SET to give a more efficient and compact nanometer scale circuit. The designed arbiter circuit utilizes the Coulomb blockade oscillation characteristics of SET to give better performances in terms of circuit area, power dissipation and delay. MIB compact model and BSIM4.6 model is used to design the circuit and the functionality of the result is verified by Tanner spice simulator.

A Comparative Study of Single Electron Threshold Logic-Based and SET-MOS Hybrid Based Half Subtractor

In the present work, we have implemented a half subtractor using two different approaches, single electron threshold logic-based approach and SET-MOS hybrid approach. The logic operation of the designed circuits is tested using TSPICE and Monte–Carlo-based simulation tool SIMON. The stability of the threshold logic-based circuit is tested using the stability plots. Further we compared the performances to characterize the advantages and disadvantages of both the approaches. The proper functioning of both the circuits is successfully verified by observing the simulated output waveforms.

Error probability independent delay analysis of single electronics circuits

Summary This study based on Poisson process and orthodox theory of single electron tunneling for the first time proposes an error probability independent delay model for delay calculation of single electronics circuits, involving multiple tunneling events. The Poisson process assumes that the tunneling events are independent of each other, but in real single electronics circuits they are correlated through space and time, so this effect has been considered and included in the proposed model. The dependence of tunneling rates on the logic transition is thoroughly investigated. Finally, the model is applied to different logic gates, and the result is compared with the well known Monte Carlo approach to prove the accuracy of the proposed model.

Millimeter and Sub-millimeter wave Response of Two-Dimensional Hot Electrons in double delta doped GaAs Quantum Well

Millimeter and sub-millimeter wave response of two-dimensional hot electrons in double delta doped GaAs quantum well is studied here incorporating deformation potential acoustic, polar optic, ionized background and remote impurity scatterings in the framework of heated drifted Fermi-Dirac distribution function. The inclusion of delta doping is found to enhance the two-dimensional electron density which in turn improves the ac mobility in the GaAs quantum wells thereby providing scope of getting higher speed devices in future.