N. Murali

A novel application of Lucy-Richardson deconvolution: bearing fault diagnosis

The main hindrance in easy detection of bearing faults from vibration data is that the signal is noise ridden, and only an efficient method for noise reduction will effectively bring out the fault characteristics. This paper proposes a novel method for such noise reduction using Lucy–Richardson deconvolution, which is an iterative technique for deblurring images. Its application in signal processing more specially in bearing fault diagnosis is being studied in this paper. The characteristics of this deconvolution with different shapes of point spread function and their effectiveness are also shown.

Development of FPGA based IIR Filter implementation of 2-degree of Freedom PID controller

In this paper an attempt has been made to present the development of FPGA based IIR Filter implementation of PID controller which takes care of issues like the derivative kick, integral saturation, bumpless transfer from manual to automatic mode. The paper starts with an overview of the FPGA technology and motivation for using it in control and then moves on into the philosophy of closed loop PID control. The design issues are explored next using MATLAB and SYSTEM GENERATOR tools. Finally simulation results are presented. Also a performance comparison between the conventional PID control and the 2-Degree of Freedom PID control for a second order process is presented.

An intuitive approach to determine test adequacy in safety-critical software

Safety-critical software must adhere to stringent quality standards and is expected to be thoroughly tested. However, exhaustive testing of software is usually impractical. The two main challenges faced by a software testing team are generation of effective test cases and demonstration of testing adequacy. This paper proposes an intuitive and conservative approach to determine the test adequacy in safety-critical software. The approach is demonstrated through a case study: the core temperature monitoring system of a nuclear reactor. We combine conservative test coverage of unique execution path test cases, and the results from mutation testing to determine the test adequacy. Although mutation testing is a powerful technique, the difficulty in identifying equivalent mutants has limited its practical utility. To gain confidence on the computed test adequacy: (i) faults during mutation testing must be induced at all possible execution paths of the code, (ii) properties of unkilled mutants must be studied, and (iii) all equivalent mutants must be detected. In this regard; results of static, dynamic and coverage analysis of the mutants is presented, and a technique to identify the likely equivalent mutants is proposed.

DSDPC: Delay signatures at different process corners based hardware trojan detection technique for FPGAs

In applications such as nuclear power plant, space and military, safety critical systems play an important role, where security is one of the crucial design parameters. Similar to software Trojans (virus), Hardware Trojans (HT) are raising security concerns in recent years. HTs are malicious additions or modifications to existing circuit elements which are implemented either as always on or triggered only under certain conditions, to disable functionality, reduce reliability and leak valuable information from the integrated chip. In this paper, we consider the scenario of HTs inserted in field programmable gate array (FPGA) devices during field operating conditions and propose a delay signature based HT detection technique. Static timing analysis is performed to measure the delay signatures of original netlist with that of netlist extracted from field configuration bit file. Since the results of electronic design automation tools are repetitive, we compare both the delay signatures and any deviation will indicate that configuration bit file/ netlist file of the original design is altered. To increase the detection efficiency, we perform static timing analysis at various process corners such as slow, typical and fast corners (at different voltage and temperature combinations) which allows us to measure the best and worst circuit delay values. Using this property, we performed simulations with Xilinx ISE tool by targeting standard benchmark circuits on Xilinx device. Experimental results reflected the difference in delay signatures if configuration bit file is tampered with in the field. The delay difference between with and without HT circuit is enhanced from slow to fast process corner, which in turn increased the HT detection efficiency.

Real Time Computer for plugging indicator control of Prototype Fast Breeder Reactor

Prototype Fast Breeder Reactor (PFBR) is in the advanced stage of construction at Kalpakkam, India. Liquid sodium is used as coolant to transfer the heat produced in the reactor core to steam water circuit. Impurities present in the sodium are removed using purification circuit. Plugging indicator is a device used to measure the purity of the sodium. Versa Module Europa bus based Real Time Computer (RTC) system is used for plugging indicator control. Hot standby architecture consisting of dual redundant RTC system with switch over logic system is the configuration adopted to achieve fault tolerance. Plugging indicator can be controlled in two modes namely continuous and discontinuous mode. Software based Proportional-Integral-Derivative (PID) algorithms are developed for plugging indicator control wherein the set point changes dynamically for every scan interval of the RTC system. Set points and PID constants are kept as configurable in runtime in order to control the process in very efficient manner, which calls for reliable communication between RTC system and control station, hence TCP/IP protocol is adopted. Performance of the RTC system for plugging indicator control was thoroughly studied in the laboratory by simulating the inputs and monitored the control outputs. The control outputs were also monitored for different PID constants. Continuous and discontinuous mode plots were generated.

An Intuitive Signal Processing Approach for Temperature Fluctuations in Fuel Subassemblies

paper describes the approach towards signal processing characteristics for temperature fluctuations from a fast thermocouple located above fuel subassemblies of fast reactor. Simulated temperature profile denoting various power levels was fed to the FPGA and the RMS value at each power level was calculated in real time. The technique mentioned in the paper helps in the analysis of reactor power and also fluctuation in it due to subassembly blockage. Altera Cyclone III FPGA was used as target device for Terasic DE0 board. Keywordsfluctuations, root mean square, subassembly. Fast reactor.

Designing fault-tolerant real-time computer systems with diversified bus architecture for nuclear power plants

Fault-tolerant real-time computer (FT-RTC) systems are widely used to perform safe operation of nuclear power plants (NPP) and safe shutdown in the event of any untoward situation. Design requirements for such systems need high reliability, availability, computational ability for measurement via sensors, control action via actuators, data communication and human interface via keyboard or display. All these attributes of FT-RTC systems are required to be implemented using best known methods such as redundant system design using diversified bus architecture to avoid common cause failure, fail-safe design to avoid unsafe failure and diagnostic features to validate system operation. In this context, the system designer must select efficient as well as highly reliable diversified bus architecture in order to realize fault-tolerant system design. This paper presents a comparative study between CompactPCI bus and Versa Module Eurocard (VME) bus architecture for designing FT-RTC systems with switch over logic system (SOLS) for NPP.

A time-frequency analysis of temperature fluctuations in a fast reactor

Reactor power estimation in fast reactors through neutronics is the most popular technique. However, it needs caliberation by temperature readings and the neutron flux is low at core periphery. Also, for any revised core loading pattern, neutron leakage may decrease. Hence, lesser number of neutrons reach ex-core detectors.This paper proposes a method to give an estimate to power by using temperature fluctuations in the central subassembly of the reactor. Time-Frequency analysis of temperature fluctuations using SCILAB is performed here. The coolant flow is considered almost constant throughout the analysis. The results indicate that the fluctuation level increases with reactor power. The proposed method can be used additionally for reactor power estimation.

Convenient and elegant HCI features of PFBR operator consoles for safe operation

Prototype Fast Breeder Reactor (PFBR) is liquid Sodium cooled, mixed oxide fuelled, fast breeder reactor being built in Kalpakkam, India. This is a first of its kind in India by which we enter into the second stage of the 3-stage nuclear program in commercial scale. Three layered Distributed Digital Control System (DDCS) architecture was decided to be implemented for this reactor. The Graphical User Interface (GUI) for the Central Control Room in the DDCS architecture is to be developed using Qt. Considering the importance of safety in Nuclear Plants, the GUI of PFBR has to be safe, simple and unambiguous. This paper describes the structure and methodology of the GUI to provide ease and safe operation and discusses about such a development of GUI. It also discusses the operator and computer limitations and the method of achieving a balance between them with Human Computer Interaction (HCI). In this process, the specifications for a HCI development are structured. The implementation of such a HCI with Qt software is also elaborated. A Case Study with Sodium Fill & Drain system is mimicked as per the specifications defined.

Design & development of soft-core processor based remote terminal units for nuclear reactors

Remote Terminal Units (RTUs) are single board, real time remote data acquisition & control systems that are used in Fast Breeder Reactors to acquire analog/digital signals [like voltage, signal inputs from surface thermocouple, leak detector & limit switches], sends digitized data packets over Ethernet to the nearest Local Control Centre (LCC) and generate control outputs in the form of potential free contacts during all states of the reactor operation. The design implementation concepts of soft-core processor based RTUs where TSK51 (a processor IP core from Altium) is used in place of conventional microcontroller along with other glue logic coded in VHDL thereby implementing complete digital logic of the embedded system in a FPGA is being discussed in this paper. This has enabled to overcome the problem of obsolescence of components along with the added advantage of improved reliability and reduced power consumption, which is proven in the last part of the paper. This paper also demonstrates the use of Altium designer software and Altium Nanoboard [Development Kit], which is used in the entire development process, starting from IP cores based development on FPGAs, embedded software development for the IP cores and overall PCB designing.