Pavlos Maniotis

Optical Buffering for Chip Multiprocessors: A 16GHz Optical Cache Memory Architecture

We demonstrate a 16GHz physical layer optical cache memory architecture for direct mapping associativity, organized in four cache lines with every line being capable of storing two bytes of optical data. WDM formatting of both the memory address and the optical data words is exploited, while the proposed design relies on the interconnection of subsystems that comprise experimentally proven optical building blocks. The performance of the optical cache is evaluated via physical layer simulations showing successful functionality both during Read and Write operation. Going a step further and considering a higher capacity optical cache module, we present its impact when performing with true processor workload benchmarks in Chip Multiprocessor configurations, employed as a L1 cache shared among multiple cores. Its performance is compared with the conventional electronic CMP topology, where dedicated L1 electronic caches and a shared L2 cache are used, showing that the use of optical 16GHz cache can lead to performance speed-up up to 40% while reducing the cache total capacity requirements by 84%. With optical interconnects having already resulted to high-bandwidth CPU-memory bus solutions, our optical cache architecture forms a fully compatible system solution for bridging the gap between optically connected CPU-cache schemes and high-speed optical RAM cell solutions.

Client-weighted medium-transparent MAC protocol for user-centric fairness in 60 GHz radio-over-fiber WLANs

We present a novel client-weighted mediumtransparent medium access control (CW-MT-MAC) protocol with enhanced fairness service delivery properties accompanied by a low-loss remote access unit (RAU) architecture for use in indoor, Gbps-capable, 60 GHz radio-over-fiber (RoF) wireless local area networks (WLANs). Our approach relies on incorporating a client-weighted algorithm (CWA) in the optical capacity allocation mechanism employed in the MT-MAC scheme, so as to distribute the available wavelengths to the different antenna units according to the total number of active users served by each individual antenna. The protocols throughput and delay fairness characteristics are evaluated and validated through both simulations and analytic modeling for saturated network traffic operational conditions. In addition, extended simulation-based performance analysis for nonsaturated network conditions and for different end-user distributions, traffic loads, and available optical wavelengths at 1 Gbps data rates is presented. Our results confirm that complete throughput equalization can be achieved even for highly varying user population patterns when certain wavelength availability conditions are satisfied. At the same time, the presented scheme manages to equalize the average packet delays amongst packets generated by all RAUs while concurrently dropping the packet delay variation metric that is essential for quality of service delivery. Finally the proposed RAU design reduces insertion losses by almost 14 dB compared to RAU elements used in MT-MAC-compatible bus networks, extending in this way the number of supported RAUs by an order of magnitude and enabling the formation of extended-reach, high-speed RoF WLANs.

A novel chip-multiprocessor architecture with optically interconnected shared L1 optical cache memory

We demonstrate a system-level CMP architecture where optical cache memories are shared among multiple processing cores through optical buses. System-level simulations show 25-45% execution time improvement and significant capacity requirements reduction through simpler memory hierarchy.

An Optical Content Addressable Memory Cell for Address Look-Up at 10 Gb/s

We propose and experimentally demonstrate the first all-optical content addressable memory (CAM) cell that comprises an all-optical monolithically integrated InP flip-flop and an optical XOR gate. The experimental results reveal error-free operation at 10 Gb/s for both content addressing and content writing operations. The potential of these memory architectures to allow for up to 40-Gb/s operation could presumably lead to fast CAM-based routing applications by enabling all-optical address look-up schemes.

Throughput and delay fairness through an agile medium-transparent MAC protocol for 60GHz fiber-wireless LAN networks

We demonstrate a novel Medium-Transparent MAC (MT-MAC) protocol with enhanced end-user service delivery fairness properties for use in Gbps capable, 60 GHz Fiber- Wireless (FiWi) LAN networks. Our approach relies on incorporating a Client Weighted Algorithm (CWA) in the optical capacity allocation mechanism employed in the MT-MAC scheme, so as to distribute the available wavelengths to the different antenna units according to the total number of active users served by each individual antenna. The protocols throughput fairness characteristics are confirmed through extensive simulations for different end-users distributions, varying traffic loads and multiple optical wavelength availabilities at 1 Gbps data rates. The presented results show that complete throughput and delay equalization can be achieved even for highly varying user population patterns among the different antenna units when certain wavelength availability conditions are satisfied. The performance of the proposed protocol has been compared with respective results obtained by the state-of-the-art MT-MAC scheme where a round-robin arbitration algorithm is used, clearly confirming the increased fairness capabilities of our approach. In addition, the proposed scheme is simple and remains clearly distinct from the wireless capacity arbitration process, highlighting in this way the high-level agility and flexibility of the MT-MAC platform for use in high-speed 60 GHz FiWi LANs.

Performance analysis and layout design of optical blades for HPCs using the OptoBoard-Sim simulator

We demonstrate the Optical Board Simulator platform for optical PCB layout design and performance evaluation. Performance of two optical Blades is compared to CRAY-XK7 Blade for the FFTW benchmark, revealing significant throughput and latency improvements.

First demonstration of an optical content addressable memory (CAM) cell at 10 Gb/s

We experimentally demonstrate the first all-optical Content Addressable Memory (CAM) cell, employing a monolithically integrated InP Flip-Flop and a SOA-MZI XOR gate. Error-free operation during Write operation and Content Addressing is achieved at 10 Gb/s.

All-Optical Tag Comparison for Hit/Miss Decision in Optical Cache Memories

An all optical multi-wavelength tag comparator unit followed by a semiconductor optical amplifier-read access gate (SOA-RAG) is presented for all-optical cache memory architectures. Proof-of-principle operation of the Tag Comparison (TC) circuit as a dual-bit tag-comparison stage is presented by exploiting cross-phase modulation-based XOR logic gates based on SOA-Mach-Zehnder interferometers (SOA-MZIs), in order to decide upon a cache hit or cache miss operation, while the two SOA-MZI outputs control the ON/OFF cross-gain-modulation of the SOA-RAG unit. Experimental error free operation is demonstrated for a 8 × 10-Gb/s wavelength division multiplexing (WDM) formatted optical word signal and a 4 × 10-Gb/s WDM tag.

WDM-enabled optical RAM and optical cache memory architectures for Chip Multiprocessors

The rapid increase in processor throughput is currently exceeding the electronic memory speed progress, forming the well-known “Memory Wall” problem, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work spanning from WDM-enabled optical RAM bank architectures with optical all-passive row/column decoder modules to a complete 16GHz optical cache memory physical layer design for Chip Multiprocessor configurations and up to the Si-based integrated optical RAM cell architectures currently pursued within the FP7 RAMPLAS project.

Optical interconnect and memory technologies for next generation computing

We demonstrate recent advances in the area of optical RAM-based cache memory technology and in the area of optical interconnect technologies for allowing the deployment of a disintegrated computational setting where off-chip optical cache modules can be connected to cache-light Chip Multiprocessors and DRAM modules. We report on recent experimental results obtained within the FP7 project RAMPLAS and we discuss the disintegration roadmap relying on optical PCB technologies and Si-integrated AWGR and transceiver chips pursued within the recently started project ICT-STREAMS. Finally, we demonstrate the application of optical memory setups in routing applications by proposing optical CAM memories towards the implementation of complete ultra-fast routing look-up tables directly in the optical domain.