N. S. Nagaraj

Benchmarks for interconnect parasitic resistance and capacitance

Interconnect parasitics are dominating circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors. Typically, researchers and designers have been using pre-defined set of structures to validate the accuracy of interconnect models and parasitic extraction tools. Unlike industry benchmarks on circuits such as MCNC benchmarks, no benchmarks exist for interconnect parasitics. This paper discusses the issues in accurate interconnect modeling for 130 nm and below copper/ultra low-k technologies. A set of benchmark structures that could be used to validate accuracy and compare parasitic extraction tools is proposed. Silicon results from 130 nm technology are presented to illustrate the usefulness of these benchmarks. Results of application of these benchmarks to compare parasitic extraction tools are presented to demonstrate systematic validation of resistance and capacitance extraction.

BEOL variability and impact on RC extraction

Historically, back end of line (BEOL) or interconnect resistance and capacitance have been viewed as parasitic components. They have now become key parameters with significant impact on circuit performance and signal integrity. This paper examines the types of BEOL variations and their impact on RC extraction. The importance of modeling systematic effects in RC extraction is discussed. The need for minimizing the computational error in RC extraction before incorporating random process variations is emphasized.

Crosstalk noise verification in digital designs with interconnect process variations

Interconnect parasitics are playing a significant role in design and analysis in deep sub-micron (DSM) technologies. Interconnect process variations could play a significant role in achieving predictable yield. Crosstalk noise is one of the increasingly important careabouts in DSM designs. In this paper, a practical method to analyze the crosstalk noise effects with interconnect process variations using corner-based approach is described. The results from application of this method on a large DSP design implemented in 0.18/spl mu/ technology is presented. Application of the proposed method resulted in detection of a new worst case interconnect process corner that was not included in the design methodology.

Statistical Analysis of Capacitance Coupling Effects on Delay and Noise

Statistical static timing analysis (SSTA) tools have mostly addressed the process variations of devices and lumped interconnect RC effects. This paper provides an overview of interconnect process variations of capacitive coupling and its effect on crosstalk delay and noise. The correlations among parallel plate, lateral and total capacitance is shown. Correlations between resistance and capacitance are illustrated to enable development of a simple and efficient model for delay and noise analysis. Experimental results are shown to validate the assumptions on the linearity of sensitivity of delay and noise to process variations. A methodology to account for process variations in crosstalk delay and noise is proposed

The impact of inductance on transients affecting gate oxide reliability

Ringing due to inductance has an increased significance on gate oxide reliability (GOR), as failure rate is exponentially dependent on the effective voltage stress. Unlike lumped capacitance (C), self-inductance (L) itself has an impact on GOR failure rate. An added complexity in parasitic inductance extraction is that the inductance matrix is much larger than the capacitance matrix, as mutual inductance terms (K) decay slowly with distance. A comparative modeling study of the dependence of GOR failure rate on RC, RCL and RCLK effects is presented. A key finding from this study is that mutual inductance has a very large impact on GOR failure rate and needs accurate modeling. Methods to minimize GOR failure rate increases caused by parasitic inductance are discussed. This embedded tutorial covers the theory of Gate Oxide Reliability, mathematical approximations for estimating failure rates, theory of inductance modeling and a detailed study of the impact of inductance on GOR.

A practical approach to crosstalk noise verification of static CMOS designs

In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. This paper provides an overview of the issues related to crosstalk noise in static CMOS designs and presents a practical approach to full-chip crosstalk noise verification. A grouping based method is described for identification of potential victims and associated aggressors, in the absence of timing information. Results from crosstalk verification of a large DSP design is presented.

Interconnect modeling for copper/low-k technologies

Interconnect parasitics are significant and complex components of circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. In this tutorial, four key aspects of copper/low-k interconnect process are discussed: Non-linear resistance, Selective Process Bias (SPB), dummy (fill) metal and process variations. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors. Techniques used in parasitic extraction to model the copper/low-k effects are discussed in detail. Techniques to measure resistance and capacitance in silicon and correlating them to parasitic extraction tools are presented to demonstrate systematic validation interconnect parasitics.

OPSYN - OASYS Based Pseudosynthesis Tool

Design of analog circuits has been a time consuming lob over the years.The reusability of existing designs is often confined to small groups. This paper describes a knowledge based pseudosynthesis tool, to explore the existing design styles and modify them suitably to meet the design objectives and hence make the design knowledge global. This tool combines the valuable knowledge of IC designers, recent advances in technology and processes, characterization and optimization capabilities of TI-OASYS (Optimization and analysis system) to synthesise circuits. It is completely general in the sense that it can handle either analog circuits or digital circuits but is more meaningful in the analog domain, since algorithmic solutions rather than knowledge based solutions are found to be more effective in digital environment. OPSYN has the capability to choose among various alternative design modules to meet the design objectives. It handles CMOS and BiCMOS circuits. The generality of circuits that can be synthesized, ease of adding new circuits to the OPSYN library and selection of best among the design modules make OPSYN a powerful knowledge based pseudosynthesis tool. Experimental runs on an opamp and a comparator have shown that OPSYN produces good results to meet reasonable design objectives.

What's cool for the future of ultra low power designs?

Ultra low power and energy efficiency requirements are common to most IC designs today. Requirements range from extending battery life to operating on harvested energy, with applications ranging from consumer electronics to medical applications. Design methodologies have evolved over the past decade to cater to low power designs. This panel will discuss the design methodology challenges in the next generation ultra low power and energy efficient IC designs, covering EDA roadmap, low power standards, and design and verification flows.

Interconnect process variations: theory and practice

Summary form only for tutorial. Historically, transistor process variations have been studied in great detail. As interconnect becomes a significant portion of circuit performance, signal integrity, power integrity and chip reliability, study of interconnect process variations has gained increased importance. This paper provides a comprehensive overview of types and sources of all aspects interconnect process variations, including via, contact, metal, dielectric barriers and low-k dielectrics. Chemical mechanical polishing (CMP) induced variations and etch induced variations in metal topography are covered. Both systematic and random process variations are discussed. Impact of these interconnect process variations on RC delay, circuit delay, crosstalk noise, voltage drop and EM are discussed. Foundations for statistical parasitic extraction and results from correlation to silicon are discussed. Methods to determine intra-level/inter-level variations and their impact on potential circuit hazards are covered.