D. Falchieri

Very fast rate 2-input fuzzy processor for high energy physics

The paper explains the design and the realization of a small size high-speed fuzzy processor. The processor goal is to give more flexibility to the front-end electronics for high-energy physics experiments. The chip can be applied as a general purpose data analyzer; particularly for analyzing and reducing on-line the data coming from detectors. The application of a fuzzy processor to this field allows rejecting redundant data in a very short time. The design of the fuzzy processor has been done using VHDL language; it is cell-based and has been implemented with Alcatel 0.35 µm CMOS VLSI technology. The chip architecture is pipelined with a clock frequency of 133 MHz; consequently the processing rate is 30 ns since only four active rules are processed. The chip size is 3 mm2 and the total power consumption is 200 mW with 3, 3 V of voltage supply.

Characterization of the ALICE Silicon Drift Detectors using an infrared laser

The Inner Tracking System of the ALICE experiment at LHC uses Silicon Drift Detectors in two cylindrical layers located at radial distance of ≈ 15 and ≈ 24 cm from the beam axis. The spatial resolution of silicon drift detectors can be strongly affected by inhomogeneities of the doping concentration, temperature effects and non-linearity of the drift potential distribution. Before the detector commissioning, an extensive study and characterization of all the produced detectors has been performed. For this purpose, a specific measuring station, based on a laser mapping system, has been developed.

The IBL readout system

The first upgrade for the ATLAS Pixel Detector will be an additional layer, which is called IBL (Insertable B-Layer). To readout this new layer, built from new electronics, an update of the readout electronics is necessary. The aim is to develop a system which is capable to read out at a higher bandwidth, but also compatible with the existing system to be integrated into it. This paper describes the necessary development to reach a new readout system, concentrating on the requirements of a newly designed Back of Crate card as the optical interface in the counting room.

Proposal for a readout driver card for the ATLAS Insertable B-Layer

An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design and it will be installed by Phase I. New front-end readout ASICs fabrication (FE-I4) will replace the previous chips in this layer. The new system features higher readout speed — 160Mb/s per ASIC — and simplified control. The current data acquisition chains are composed of front-end and readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). This paper presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS TDAQ system.

A PowerPC-based control system for the Read-Out-Driver module of the ATLAS IBL

The ATLAS experiment at LHC planned to upgrade the existing Pixel Detector with the insertion of an innermost silicon layer, called Insertable B-layer (IBL). A new front-end ASIC has been foreseen (named FE-I4) and it will be read out with improved off-detector electronics. In particular, the new Read-Out Driver card (ROD) is a VME-based board designed to process a four-fold data throughput. Moreover, the ROD hosts the electronics devoted to control operations whose main tasks are providing setup busses to access configuration registers on several FPGAs, receiving configuration data from external PCs, managing triggers and running calibration procedures. In parallel with a backward-compatible solution with a Digital Signal Processor (DSP), a new ROD control circuitry with a PowerPC embedded into an FPGA has been implemented. In this paper the status of the PowerPC-based control system will be outlined with major focus on firmware and software development strategies.

Charge collection in the Silicon Drift Detectors of the ALICE experiment

A detailed study of charge collection efficiency has been performed on the Silicon Drift Detectors (SDD) of the ALICE experiment. Three different methods to study the collected charge as a function of the drift time have been implemented. The first approach consists in measuring the charge at different injection distances moving an infrared laser by means of micrometric step motors. The second method is based on the measurement of the charge injected by the laser at fixed drift distance and varying the drift field, thus changing the drift time. In the last method, the measurement of the charge deposited by atmospheric muons is used to study the charge collection efficiency as a function of the drift time. The three methods gave consistent results and indicated that no charge loss during the drift is observed for the sensor types used in 99% of the SDD modules mounted on the ALICE Inner Tracking System. The atmospheric muons have also been used to test the effect of the zero-suppression applied to reduce the data size by erasing the counts in cells not passing the thresholds for noise removal. As expected, the zero suppression introduces a dependence of the reconstructed charge as a function of drift time because it cuts the signal in the tails of the electron clouds enlarged by diffusion effects. These measurements allowed also to validate the correction for this effect extracted from detailed Monte Carlo simulations of the detector response and applied in the offline data reconstruction.

Implementation of a bidimensional compressor for a high-energy physics experiment

CARLOSv3 is the third version of a chip that plays a significant role in the data acquisition chain of the A Large Ion Collider Experiment (ALICE) silicon drift detector (SDD). ALICE is one of the foremost high-energy physics experiments (HEPE) conducted within the Large Hadron Collider at CERN, the European Organization for Nuclear Research in Geneva. CARLOSv3 was principally designed and built for the on-line compression of the input dataset originating from a physical bidimensional silicon sensor. To compress a bidimensional dataset, a bidimensional data compressor was required. The compressor was designed for the ALICE SDD Experiment but could be applied to all experiments in which an incoming stream dataset originates from a bidimensional sensor.

A digital fuzzy processor for fuzzy-rule-based systems

In this chapter, we describe a family of fuzzy processors oriented to physics experiments. We firstly present two fuzzy processors that have already been realized; the architectures are described in detail. Then, we present a new fast digital Fuzzy Processor that has been designed on 0.7 mm digital CMOS technology. The processor implements a set of fuzzy rules created by means of a genetic fuzzy rule generator. It can process ten 7-bit input variables and carries out one 7-bit output. It may be synchronized up to a 50 MHz clock signal for an estimated power consumption slightly more than 1 W. Moreover the processing rate depends on the number of fuzzy rule and , as a rule of thumb, it can be estimated by multiplying 20 ns, which is the clock period, for the number of fuzzy rules. Also, the inside parallel-pipeline architecture is described in detail. In addition, the architecture is described with layout and data flow simulation pictures. The fuzzy logic methodologies that have been adopted are justified in terms of hardware implementation feasibility and speed requirements.

Test results of the ALICE SDD electronic readout prototypes

The first prototypes of the front-end electronic of the ALICE silicon drift detectors has been designed and tested. The integrated circuits have been designed using state-of-theart technologies and, for the analog parts, with radiation-tolerant design techniques. In this paper, the test results of the building blocks of the PASCAL chip and the first prototype of the AMBRA chip are presented. The prototypes fully respect the ALICE requirements; owing to the use of deep-submicron technologies together with radiationtolerant layout techniques, the prototypes have shown a tolerance to a radiation dose much higher than the one foreseen for the ALICE environment. Summary The design of the readout electronic for the ALICE silicon drift detector is a very challenging task, due on one side to the huge amount of data produced by those detectors (256 10-bit words for each detector anode, in the case of the ALICE SDDs ) and on the other hand to the stringent constraints in term of space, power consumption and radiation hardness. The chosen architecture is based on 2 integrated circuits, PASCAL and AMBRA. It works in two different phases: during the acquisition phase the detector signal is amplified and stored into a fast analogue memory; when the trigger signal validates the data, the readout phase starts and the analogue information in the memory is

Implementation and tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card

The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back-compatible solution (using a Digital Signal Processor) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported.