Gensuke Goto

A 54*54-b regularly structured tree multiplier

A 54-b*54-b parallel multiplier was implemented in 0.88- mu m CMOS using the new, regularly structured tree (RST) design approach. The circuit is basically a Wallace tree, but the tree and the set of partial-product-bit generators are combined into a recurring block which generates seven partial-product bits and compresses them to a pair of bits for the sum and carry signals. This block is used repeatedly to construct an RST block in which even wiring among blocks included in wire shifters is designed as recurring units. By using recurring wire shifters, the authors can expand the level of repeated blocks to cover the entire adder tree, which simplifies the complicated Wallace tree wiring scheme. In addition, to design time savings, layout density is increased by 70% to 6400 transistors/mm/sup 2/, and the multiplication time is decreased by 30% to 13 ns. >

A 4.1 ns compact 54/spl times/54 b multiplier utilizing sign select Booth encoders

A sign select Booth encoder reduces transistor count of multipliers. This encoder is applied in a 54/spl times/54 b multiplier in 0.25 /spl mu/m CMOS technology. Because of the rapid progress in VLSI design technologies, consecutive improvements in operational speed and design integration are made. As a result of these improvements, interactive real-time 3D graphics applications have become available even in personal computers.

A wafer-scale 170000-gate FFT processor with built-in test circuits

The wafer-scale 170000-gate fast Fourier transform (FFT) processor described consists of individual repeatable building blocks, each of which contains a processing element (PE) and interconnection wiring. The PE consists of a multiplier accumulator and its built-in self-test circuits. The wafer system is reconfigured by connected active blocks after block self-diagnosis. Blocks are connected using a programmable contact-hole mask. The processor performs parallel 16-bit, eight-point complex FFTs and is implemented with 725 I/O pads in triple-metal 2.3- mu m p-well CMOS technology on a 4-in. wafer. It is mounted by controlled-collapse bonding facedown on a 11.8*11.8-cm/sup 2/ substrate. >

A 4.1 ns compact 54×54 b multiplier utilizing sign select Booth encoders

A5 4 54-b multiplier with only 60 K transistors has been fabricated by 0.25- m CMOS technology. To reduce the total transistor count, we have developed two new approaches: sign-select Booth encoding and 48-transistor 4-2 compressor cir- cuits both implemented with pass transistor logic. The sign-select Booth algorithm simplifies the Booth selector circuit and enables us to reduce the transistor count by 45% as compared with that of the conventional one. The new compressor reduces the count by 20% without speed degradation. By using these new circuits, the total transistor count of the multiplier is reduced by 24%. The active size of the 54 54-b multiplier is 1.04 1.27 mm and the multiplication time is 4.1 ns at a 2.5-V power supply. ECAUSE of the rapid progress in very large scale in- tegration (VLSI) design technologies, consecutive im- provements in operational speed and design integration have been made. As a result of these improvements, interactive real-time three-dimensional (3-D) graphics applications have become available even on personal computers. In the geomet- ric conversion processes of 3-D graphics applications, huge amounts of floating point operations are required and parallel data processing is inevitable. The amount of these arithmetic operations in real-time 3-D graphics applications depends on the quality of the 3-D objects and the frame rate. For example, in the case of a screen with a 1600 1280 resolution and at 60 frames/s, if 3-D objects are formed with small polygons (25 pixels/polygon) and 80% of the entire screen is constantly being processed with 3-D objects, approximately 4 Mp/s (million polygons per second) are processed. Our evaluations so far indicate that, to achieve 1 Mp/s of 3-D geometric conversion performance, 250 to 300 MFLOPS of floating point arithmetic performance are required. Consequently, to achieve the above mentioned 4 Mp/s operation, more than 1 GFLOPS of floating point computation power is needed. In addition to 3-D graphics applications, a drastic improvement in the floating-point performance of general-purpose microprocessors and DSPs has been hoped for to meet the user demand for multimedia data processing. In such circumstances as above, a cost-effective, high-speed float-

An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit

The authors discuss the weak point of a conventional bypass circuit, or carry-skip paths in a Manchester adder, and propose a new bypass circuit and its control scheme to avoid transitory fighting that causes an intermediate voltage. A 112-b transmission gate adder is presented. It uses a group of three mutually exclusive transmission gates for the carry-skip paths and a new conditional sum generation circuit. It has an estimated propagation delay time of 8.5 ns and 6941 transistors, both of which are smaller than for conventional carry select adders. The adder is integrated into an area of 0.41*3.36 mm/sup 2/ achieved by a 0.8- mu m, triple-metal, full-CMOS process. >

A 240K transistor CMOS array with flexible allocation of memory and channels

A CMOS masterslice will be reported, covering the design of basic cells to accommodate both logic unit and memory cells, wiring channels allocated in discrete units and logic and memory blocks placed in arbitrary positions of a cell array. Implementation of a 16×16b parallel multiplier with 16b×64w SRAM and 16b×256w ROM will be compared.A CMOS masterslice containing about 240K transistors is described. A new basic cell was designed for efficient construction of both logic and memory cells. For flexible allocation of wiring channels, logic unit cells, and memory blocks, about 30000 basic cells with no dedicated channel regions are spread throughout the chip, except in the I/O region. Logic and memory blocks can be placed anywhere on the chip. A test chip, developed to investigate the feasibility of the masterslice design, reveals densities of 230 gates/mm/SUP 2/, 230 bit/mm/SUP 2/, and 1900 bit/mm/SUP 2/ for a 16/spl times/16-bit multiplier, a 1K SRAM, and a 4K ROM, respectively.

Latch-up immunity against noise pulses in a CMOS double well structure

Latch-up immunity in a CMOS double well structure against a pulsive noise when the noise is applied to the p-well has been studied both theoretically and experimentally. Agreement between them is satisfactory and the transient response has been found to be described by a two-step activation model. The dependence of the latch-up trigger current on the duration time of the noise has been extensively studied in several cases of the double well structure to deduce design criteria for CMOS VLSIs with reasonable immunity against latch-up.

Modeling and analysis of transient latchup in double-well bulk CMOS

Characteristics of transient latchup due to noise excitation through the gate of a parasitic SCR are measured and described by a new simplified model to clarify latchup immunity in a double-well CMOS with a nonepitaxial substrate. The model accounts for the effects of high-level carrier injection and base transit delays of the two parasitic transistors, and it can describe the observed latchup transient faithfully if the model parameters are given according to the predetermined procedure. The noise-pulse-width dependence of the latchup trigger current is obtained as a function of current gain, transit time, and transistor base-emitter shunt resistance to show the last one most sensitive to the trigger current. The optimum parameters with the double well are deduced from study to relate the model to structural parameters.

Influence of carrier diffusion on an anode trapped domain formation in a transferred electron device

This paper presents an influence of the electric field dependence of the diffusion coefficient of electrons (D(E) relation) on a formation of a stable domain at an anode contact in a transferred electron device. The stable domain (anode trapped domain) has been observed in a planar Gunn device experimentally, and it has been shown that a large trigger voltage is needed to launch a new domain if a preceding domain has been trapped. Computer simulations have been carried out in order to find a condition to form the trapped domain. Various D(E) relations of GaAs presented by many authors have been adopted to the simulation, and it is shown that one of these D(E) relations is suitable to describe the dynamic behaviors of electrons in GaAs. Simulated results have indicated that the trapped domain occurs in a certain range of doping density.

A wafer-scale FFT processor featuring a repeatable building block

The wafer-scale 170000-gate fast Fourier transform (FFT) processor has three features: a single repeatable building block containing a processing element (PE) and its interconnects, mask-programmable routing by the placement of contact holes, and a built-in self-test (BIST) for the PE and its interconnects. The wafer system is composed of 48 PEs selected out of a total of 88 PEs. The PE consists of a 2800-gate multiplier-accumulator and 700-gate BIST circuitry. The processor performs parallel 16-bit, 8-point complex FFT and is implemented with 725 I/O pads in triple-metal 2.3- mu m CMOS technology on a 4-inch wafer. This wafer is mounted face down on an 11.8*11.8-cm/sup 2/ substrate by solder bumps.<<ETX>>