Nader Anani

Synchronization of a Single-phase Photovoltaic Generator With the Low-Voltage Utility Grid

The increased generation of electrical energy from renewable sources and its integration into the low voltage grid have necessitated regulations governing the connection of renewable energy generators to the grid. This was deemed necessary to preserve the integrity and the correct operation of the grid. This paper presents a new architecture of a hybrid phase lock loop circuit topology for synchronizing a single-phase inverter fed from a renewable energy source such as a photovoltaic (PV) generator to the low voltage grid. The system uses a digital phase lock loop (DPLL) architecture, which is based on the arctan phase detector, driving a phase lock loop (PLL) to synchronize a PV inverter with the grid. The proposed system has been tested by simulation using simulink /matlab . The test results demonstrate the ability of the system to synchronize a PV inverter with the grid and to re-establish synchronization following a sudden perturbation in the grid voltage such as a single or a multistep change in phase. The system is digital and can be readily implemented using an FPGA (field programmable gate array) and hence can be easily embedded in a home or small scale single-phase PV inverter.

Time delay digital tanlock loop with linearized phase detector

This paper presents a time delay digital tanlock loop with a linearized phase detector (TDTL-LPD) architecture. This is achieved through replacement of the time delay unit of the TDTL by a variable delay whose phase error is controlled by a feedback mechanism driven by the output of the inverse tan phase detector. The change in this output is proportional to the changes in the input signal frequency of the system. This results in keeping the quadrature relationship between the two channels that make up the TDTL. This linearization of the phase error detector results in the improvement of the system performance when used in communication system applications such as FSK (frequency shift keying) demodulation.

Digital tanlock loop architecture with no delay

This article proposes a new architecture for a digital tanlock loop which eliminates the time-delay block. The (rad) phase shift relationship between the two channels, which is generated by the delay block in the conventional time-delay digital tanlock loop (TDTL), is preserved using two quadrature sampling signals for the loop channels. The proposed system outperformed the original TDTL architecture, when both systems were tested with frequency shift keying input signal. The new system demonstrated better linearity and acquisition speed as well as improved noise performance compared with the original TDTL architecture. Furthermore, the removal of the time-delay block enables all processing to be digitally performed, which reduces the implementation complexity. Both the original TDTL and the new architecture without the delay block were modelled and simulated using MATLAB/Simulink. Implementation issues, including complexity and relation to simulation of both architectures, are also addressed.

Adaptive TDTL using frequency and phase processing techniques

An adaptive initialization process for the first-order time delay digital tanlock loop (TDTL) is proposed. The process results in improving the system performance by widening its lock range and by having zero steady-state phase error. The proposed adaptive TDTL with zero phase error (ATDTL-ZPE) uses a feedforward initialization technique which results in freeing the loop from the frequency locking process. The loop phase detector is used only for phase locking purposes and hence result in zero steady-state phase error with a considerable improvement in the system locking range.

Improved performance second order time delay digital tanlock loop

This paper presents a second order time delay digital tanlock loop with improved locking as well as acquisition performance. The former is achieved through replacement of the delay unit of the TDTL by a variable one whose phase error is controlled by the output of the phase detector. This approach maintains the quadrature relationship between the two TDTL channels and hence results in a linearized phase detector characteristics. Fast acquisition is obtained through modification of the free running sampling frequency of digital controlled oscillator (DCO) in order to speed up the loop digital filter response. This improved architecture was tested using various input signals including FSK (frequency shift keying) and the results show an enhanced performance when compared with the original TDTL system.

Modelling and simulation of photovoltaic arrays under varying conditions

This paper presents the modelling and simulation results of the effects of varying conditions on the characteristic of a PV (photovoltaic) array with due account of its use in residential applications. The varying conditions include insolation, temperature and arbitrary partial shading. A model of a PV array is developed by modifying the model of a basic PV cell found in the SimElectronics toolbox of the Simulink/MATLAB software, which uses the two-diode model of a PV cell. The model parameters were modified to match a given set of parameters provided by a particular datasheet. The simulation results concurred with those found in the relevant datasheets. The software can be used as a computer-aided design tool to aid the design of PV arrays taking into account the effects of the said conditions.

Adaptive digital tanlock loop with no delay

This paper proposes an adaptive technique for rapid error correction of a digital tanlock loop architecture with no time delay (ANDTL) unit and with a linearized phase-detector. The ANDTL uses a feed-forward technique for early comparison between the estimated value of the input signal frequency and that of the DCO (digital controlled oscillator). The error signal resulting from the comparison is used to set the initialization of the DCO in order to match that of the incoming signal. The performance of the ANDTL architecture was evaluated by using FSK demodulation and results indicate a marked improvement in the loop acquisition time as well as its jitter in the presence of noise.

Remote condition monitoring of a PV system using an embedded web server

The architecture and construction of a simple embedded web server system with due account of its application for remote condition monitoring of a photovoltaic (PV) installation is presented. The system, which is based on a PIC18 microcontroller, uses the Internet as a medium for communications between a central control point and a PV system. It allows various parameters of a PV installation such as the temperature of an individual PV module and its open-circuit voltage to be remotely accurately measured and monitored. This permits early detection of any technical problem such as a faulty PV module to be communicated over the Internet to a desired location. Inspection of the PV system is also possible from any Internet enabled computer terminal.

Synchronization of a single-phase photovoltaic generator with the grid

This paper presents the architecture of a hybrid phase lock loop circuit topology for synchronizing a single-phase inverter fed from a renewable energy source such as a photovoltaic (PV) generator to the low voltage utility grid. The system uses a digital phase lock loop (DPLL) architecture, which is based on the arctan phase detector, driving a phase lock loop (PLL) to synchronize a PV generator with the grid. The proposed system has been tested by simulation using Simulink/Matlab. The test results, which are also presented, demonstrate the ability of the system to synchronize a PV inverter with the grid and to regain synchronization following a sudden change in the phase of the grid voltage.

Dual Time Delay Digital Tanlock Loop with improved performance

A dual Time Delay Digital Tanlock Loop (D-TDTL) topology is proposed in this work. The system consists of a stacked dual loop of which the top one acts as a Frequency Lock loop (FLL) for the bottom loop, while the latter is a phase lock loop (PLL) that enhances the overall phase of the system. The main advantage of the proposed system is the large reduction of phase noise or jitter which makes it well suited to operate in noisy environment. The performance of the D-TDTL system was demonstrated using frequency shift keying (FSK) input signal with AWGN noise.