Omar Al-Kharji Al-Ali

Time delay digital tanlock loop with linearized phase detector

This paper presents a time delay digital tanlock loop with a linearized phase detector (TDTL-LPD) architecture. This is achieved through replacement of the time delay unit of the TDTL by a variable delay whose phase error is controlled by a feedback mechanism driven by the output of the inverse tan phase detector. The change in this output is proportional to the changes in the input signal frequency of the system. This results in keeping the quadrature relationship between the two channels that make up the TDTL. This linearization of the phase error detector results in the improvement of the system performance when used in communication system applications such as FSK (frequency shift keying) demodulation.

Digital tanlock loop architecture with no delay

This article proposes a new architecture for a digital tanlock loop which eliminates the time-delay block. The (rad) phase shift relationship between the two channels, which is generated by the delay block in the conventional time-delay digital tanlock loop (TDTL), is preserved using two quadrature sampling signals for the loop channels. The proposed system outperformed the original TDTL architecture, when both systems were tested with frequency shift keying input signal. The new system demonstrated better linearity and acquisition speed as well as improved noise performance compared with the original TDTL architecture. Furthermore, the removal of the time-delay block enables all processing to be digitally performed, which reduces the implementation complexity. Both the original TDTL and the new architecture without the delay block were modelled and simulated using MATLAB/Simulink. Implementation issues, including complexity and relation to simulation of both architectures, are also addressed.

Adaptive TDTL using frequency and phase processing techniques

An adaptive initialization process for the first-order time delay digital tanlock loop (TDTL) is proposed. The process results in improving the system performance by widening its lock range and by having zero steady-state phase error. The proposed adaptive TDTL with zero phase error (ATDTL-ZPE) uses a feedforward initialization technique which results in freeing the loop from the frequency locking process. The loop phase detector is used only for phase locking purposes and hence result in zero steady-state phase error with a considerable improvement in the system locking range.

Adaptive digital tanlock loop with no delay

This paper proposes an adaptive technique for rapid error correction of a digital tanlock loop architecture with no time delay (ANDTL) unit and with a linearized phase-detector. The ANDTL uses a feed-forward technique for early comparison between the estimated value of the input signal frequency and that of the DCO (digital controlled oscillator). The error signal resulting from the comparison is used to set the initialization of the DCO in order to match that of the incoming signal. The performance of the ANDTL architecture was evaluated by using FSK demodulation and results indicate a marked improvement in the loop acquisition time as well as its jitter in the presence of noise.

Second-order TDTL with initialization process

This paper proposes an improved time delay digital tanlock loop (TDTL) system in which a feedforward loop is used to initialize the loop filter memory so as to enhance the acquisition speed of the system. The feedforward loop is used to estimate the value of the steady-state frequency of the input signal which is subsequently loaded into the memory of the loop filter. The system was simulated and tested using Simulink/Matalb using frequency step and FSK modulation. Further, the system was implemented using an FPGA and testing results indicate an ample improvement in the acquisition speed over the original TDTL system.

TDTL architecture with fast error correction technique

A new technique for fast error correction of the TDTL (time delay digital tanlock loop) is proposed. The technique is based on early comparison of the input signal frequency with that of the loop filter output. The result of this comparison is then used to select an optimum value for the loop filter output. This technique eliminates the need for continuously changing the loop filter coefficient. The major advantages of the proposed technique are a reduction in the complexity of the adaptive TDTL structure and an improvement in the loop acquisition time. The performance of the proposed system was tested using an FSK input signal and the results indicate enhanced performance compared to the conventional TDTL system.

Digital tanlock loop without a phase shifter

This paper presents an improved digital tanlock loop architecture that has linear phase detector characteristics. These characteristics were linearized by removing the fixed time delay unit in the original time delay tanlock loop (TDTL) and using a modified DCO (digital controlled oscillator). The modified DCO incorporates lookup tables to generate two outputs with quadrature relationship. The two outputs control the circuit blocks used to sample the loop input signal. The performance of the proposed system was evaluated using various input signals to assess its acquisition speed. The simulation results using Simulink/MATLAB indicate an improvement in the acquisition performance of the proposed system compared to the original TDTL. In addition, the implementation complexity of the proposed system is also improved as the realization of two DCO outputs lends itself to FPGA implementation which may be readily achieved using only one direct digital synthesizer (DDS) with two lookup tables to stores both values of sine and cosine waveforms which are used for the sampling of the input signal.

Second-order single channel digital tanlock based phase-locked loop

The design of a second-order digital phase-locked loop (DPLL) based on the time-delay digital tanlock loop (TDTL) architecture is presented. The proposed design simplifies the architecture of the TDTL by eliminating the requirement for the time delay block. In addition, the system includes a controller block whose output feeds into the arctan phase detector of the proposed system so as to optimize the acquisition time and/or the lock range of the loop. The system performance evaluation results show that it is possible to selectively optimize certain parameters of the system in order to match specific application requirements.

Performance evaluation of the time delay digital tanlock loop architectures

This article presents the architectures, theoretical analyses and testing results of modified time delay digital tanlock loop (TDTLs) system. The modifications to the original TDTL architecture were introduced to overcome some of the limitations of the original TDTL and to enhance the overall performance of the particular systems. The limitations addressed in this article include the non-linearity of the phase detector, the restricted width of the locking range and the overall system acquisition speed. Each of the modified architectures was tested by subjecting the system to sudden positive and negative frequency steps and comparing its response with that of the original TDTL. In addition, the performance of all the architectures was evaluated under noise-free as well as noisy environments. The extensive simulation results using MATLAB/SIMULINK demonstrate that the new architectures overcome the limitations they addressed and the overall results confirmed significant improvements in performance compared to the conventional TDTL system.

Tanlock loop noise reduction using an optimised phase detector

This article proposes a time-delay digital tanlock loop (TDTL), which uses a new phase detector (PD) design that is optimised for noise reduction making it amenable for applications that require wide lock range without sacrificing the level of noise immunity. The proposed system uses an improved phase detector design which uses two phase detectors; one PD is used to optimise the noise immunity whilst the other is used to control the acquisition time of the TDTL system. Using the modified phase detector it is possible to reduce the second- and higher-order harmonics by at least 50% compared with the conventional TDTL system. The proposed system was simulated and tested using MATLAB/Simulink using frequency step inputs and inputs corrupted with varying levels of harmonic distortion. A hardware prototype of the system was implemented using a field programmable gate array (FPGA). The practical and simulation results indicate considerable improvement in the noise performance of the proposed system over the conventional TDTL architecture.