Prasad V. S. Ponnapalli
Manchester Metropolitan University
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Publication
Featured researches published by Prasad V. S. Ponnapalli.
Journal of Solar Energy Engineering-transactions of The Asme | 2012
Nader Anani; Omar Al-Kharji; Prasad V. S. Ponnapalli; Saleh R. Al-Araji; Mahmoud Al-Qutayri
The increased generation of electrical energy from renewable sources and its integration into the low voltage grid have necessitated regulations governing the connection of renewable energy generators to the grid. This was deemed necessary to preserve the integrity and the correct operation of the grid. This paper presents a new architecture of a hybrid phase lock loop circuit topology for synchronizing a single-phase inverter fed from a renewable energy source such as a photovoltaic (PV) generator to the low voltage grid. The system uses a digital phase lock loop (DPLL) architecture, which is based on the arctan phase detector, driving a phase lock loop (PLL) to synchronize a PV inverter with the grid. The proposed system has been tested by simulation using simulink /matlab . The test results demonstrate the ability of the system to synchronize a PV inverter with the grid and to re-establish synchronization following a sudden perturbation in the grid voltage such as a single or a multistep change in phase. The system is digital and can be readily implemented using an FPGA (field programmable gate array) and hence can be easily embedded in a home or small scale single-phase PV inverter.
International Journal of Electronics | 2012
Omar Al-Kharji Al-Ali; Nader Anani; Saleh R. Al-Araji; Mahmoud Al-Qutayri; Prasad V. S. Ponnapalli
This article proposes a new architecture for a digital tanlock loop which eliminates the time-delay block. The (rad) phase shift relationship between the two channels, which is generated by the delay block in the conventional time-delay digital tanlock loop (TDTL), is preserved using two quadrature sampling signals for the loop channels. The proposed system outperformed the original TDTL architecture, when both systems were tested with frequency shift keying input signal. The new system demonstrated better linearity and acquisition speed as well as improved noise performance compared with the original TDTL architecture. Furthermore, the removal of the time-delay block enables all processing to be digitally performed, which reduces the implementation complexity. Both the original TDTL and the new architecture without the delay block were modelled and simulated using MATLAB/Simulink. Implementation issues, including complexity and relation to simulation of both architectures, are also addressed.
information sciences, signal processing and their applications | 2010
Omar Al-Kharji Al-Ali; Saleh R. Al-Araji; Nader Anani; Mahmoud Al-Qutayri; Prasad V. S. Ponnapalli
An adaptive initialization process for the first-order time delay digital tanlock loop (TDTL) is proposed. The process results in improving the system performance by widening its lock range and by having zero steady-state phase error. The proposed adaptive TDTL with zero phase error (ATDTL-ZPE) uses a feedforward initialization technique which results in freeing the loop from the frequency locking process. The loop phase detector is used only for phase locking purposes and hence result in zero steady-state phase error with a considerable improvement in the system locking range.
ieee sarnoff symposium | 2010
Saleh R. Al-Araji; O. Al-Kharji Al-Ali; Mahmoud Al-Qutayri; Nader Anani; Prasad V. S. Ponnapalli
This paper presents a second order time delay digital tanlock loop with improved locking as well as acquisition performance. The former is achieved through replacement of the delay unit of the TDTL by a variable one whose phase error is controlled by the output of the phase detector. This approach maintains the quadrature relationship between the two TDTL channels and hence results in a linearized phase detector characteristics. Fast acquisition is obtained through modification of the free running sampling frequency of digital controlled oscillator (DCO) in order to speed up the loop digital filter response. This improved architecture was tested using various input signals including FSK (frequency shift keying) and the results show an enhanced performance when compared with the original TDTL system.
Journal of Electronic Imaging | 2001
R. Deloughry; Elaine Pickup; Prasad V. S. Ponnapalli
The subject of pneumatic conveying of solids is a complex one. The flow regime present in a conveying system is dependent upon: the size and shape of the particles to be conveyed, the geometry and orientation of the conveying pipe, the relative densities of the solid and the conveying air. The variable parameters present are the velocity of the conveying air and the solids mass flow rate. The variation of these two factors dictates the presence of either dilute or dense phase flow. At Manchester Metropolitan University a pneumatic conveying system transporting polyethylene nibs, was used to investigate the implementation of a Proportional and Integral control system using a tomographic imaging system in the feedback loop. The aim of the investigative work was to achieve control of the air velocity and solids loading factor for the conveying system to maintain dilute phase flow at a prescribed level. The solids material conveyed was sensed using a PC based electrical tomographic imaging system and this was used to control the air velocity in the conveying system.
conference on computer as a tool | 2011
Nader Anani; O. Al-Kharji Al-Ali; Prasad V. S. Ponnapalli; Saleh R. Al-Araji; Mahmoud Al-Qutayri
This paper presents the architecture of a hybrid phase lock loop circuit topology for synchronizing a single-phase inverter fed from a renewable energy source such as a photovoltaic (PV) generator to the low voltage utility grid. The system uses a digital phase lock loop (DPLL) architecture, which is based on the arctan phase detector, driving a phase lock loop (PLL) to synchronize a PV generator with the grid. The proposed system has been tested by simulation using Simulink/Matlab. The test results, which are also presented, demonstrate the ability of the system to synchronize a PV inverter with the grid and to regain synchronization following a sudden change in the phase of the grid voltage.
conference on computer as a tool | 2011
O. Al-Kharji Al-Ali; Nader Anani; Prasad V. S. Ponnapalli; Saleh R. Al-Araji; Mahmoud Al-Qutayri
A dual Time Delay Digital Tanlock Loop (D-TDTL) topology is proposed in this work. The system consists of a stacked dual loop of which the top one acts as a Frequency Lock loop (FLL) for the bottom loop, while the latter is a phase lock loop (PLL) that enhances the overall phase of the system. The main advantage of the proposed system is the large reduction of phase noise or jitter which makes it well suited to operate in noisy environment. The performance of the D-TDTL system was demonstrated using frequency shift keying (FSK) input signal with AWGN noise.
ASME 2011 5th International Conference on Energy Sustainability, Parts A, B, and C | 2011
Nader Anani; Omar Al-Kharji; Prasad V. S. Ponnapalli; Saleh R. Al-Araji; Mahmoud Al-Qutayri
The increased generation of electrical energy from renewable sources and its integration into the low voltage grid, have necessitated regulations governing the connection of renewable energy generators to the grid. This was deemed necessary to preserve the integrity and the correct operation of the grid. This paper presents a new architecture of a hybrid phase lock loop circuit topology for synchronizing a singlephase inverter fed from a renewable energy source such as a photovoltaic (PV) generator to the low voltage grid. The system uses a digital phase lock loop (DPLL) architecture, which is based on the arctan phase detector, driving a phase lock loop (PLL) to synchronize a PV inverter with the grid. The proposed system has been tested by simulation using Simulink/Matlab. The test results demonstrate the ability of the system to synchronize a PV inverter with the grid and to re-establish synchronization following a sudden perturbation in the grid voltage such as a single or a multi-step change in phase. The system is digital and can be readily implemented using an FPGA (field programmable gate array) and hence can be easily embedded in a home or small scale single-phase PV inverter.
International Conference on Innovative Techniques and Applications of Artificial Intelligence | 2008
Abdel-Razzak Natsheh; Prasad V. S. Ponnapalli; Nader Anani; Atef El-Kholy
Diagnosis of Sinus condition is considered a difficult task in medical clinics due to the similar nature of the symptoms and the complexity of the images (e.g. plane of image, resolution) obtained using either CT-Scan. Discussions with consultant doctors and radiologists working in this area pointed at the need for a computer-based analysis and diagnosis tool that could be used as an aid to experts for diagnosing sinus diseases. There are a number of tools using traditional image processing techniques that are primarily useful for enhancing images. For an integrated system with potential diagnostic abilities artificial neural networks are good candidates that can combine image processing and diagnostic abilities in a single system. This paper presents the background and preliminary results in the development of an automated tool for the analysis and diagnosis of sinus conditions. The data used is in the form of CT scan images of sinus. Technology based on traditional image processing and Artificial Neural Networks (SOM) are explored for image processing and diagnosis. Anonymous CT-images of Sinuses were obtained from a local hospital. Preliminary results show that the proposed system has the potential to be a useful tool for clinicians in the areas of diagnosis and training of junior doctors.
international conference on electronics, circuits, and systems | 2010
Omar Al-Kharji Al-Ali; Nader Anani; Prasad V. S. Ponnapalli; Mahmoud Al-Qutayri; Saleh R. Al-Araji
A new technique for fast error correction of the TDTL (time delay digital tanlock loop) is proposed. The technique is based on early comparison of the input signal frequency with that of the loop filter output. The result of this comparison is then used to select an optimum value for the loop filter output. This technique eliminates the need for continuously changing the loop filter coefficient. The major advantages of the proposed technique are a reduction in the complexity of the adaptive TDTL structure and an improvement in the loop acquisition time. The performance of the proposed system was tested using an FSK input signal and the results indicate enhanced performance compared to the conventional TDTL system.