Li-Kong Wang

On-chip decoupling capacitor design to reduce switching-noise-induced instability in CMOS/SOI VLSI

The supply noise from the packaging of CMOS/SOI circuits can cause performance degradation, reliability reduction and even loss of circuit functionality due to the device latch-up problem. By properly adding on-chip decoupling capacitors in the proximity of the circuitry, we can effectively alleviate the switching noise problem and improve the performance of CMOS/SOI circuits.

Thermal management for high performance integrated circuits with non-uniform chip power considerations

Thermal management for nonuniform chip power integrated circuits is studied. Circuit chip power analysis was used to generate nonuniform chip power and computational fluid dynamics (CFD) techniques are used to calculate the chip temperature. This paper also presents an integrated thermomechanical analysis of a ceramic ball grid array (CBGA) single chip module (SCM) system under chip power loads. A three-dimensional finite element model (FEM) was used for the sequential heat transfer and mechanical analyses to predict the temperature gradients and associated structural response of stress and deformation of the SCM. The thermomechanical analysis results are used to examine the integral effect of chip power loading conditions and of two design parameters, the substrate and cap materials, on the structural integrity of the modeled CBGA SCM system.

A low power high speed error correction code macro using complementary pass transistor logic circuit

This paper describes the design and implementation of the complementary pass transistor logic (CPL) circuit in a CMOS macro design. The power, speed and noise margin of pass-transistor logic circuits are evaluated and the transistor sizes are optimized for noise margin and circuit performance. This circuit has been successfully implemented in a 64-bit Error Correction Code (ECC) and parity checking macro in the IBM S/390 CMOS processor and significantly improves the power and speed of the ECC macro performance.

Integrated electro-thermomechanical analysis of nonuniformly chip-powered microelectronic system

Abstract An integrated electrical, fluid flow and thermomechanical analysis is presented to study a product reliability and thermal management solution in an actual or nonuniform chip power distribution of an integrated circuit device in a realistic system application environment. This study aims to improve the existing limitations both on electrothermal analysis where simplified thermal boundary conditions is mostly used and on the current thermal and fluid flow analysis where uniform chip power is widely used to calculate the temperature. In this approach, the localized on-chip power distribution is obtained by using a transistor-level circuit model for simulating the interaction between the macro and functional blocks. A computational fluid dynamics analysis is used to calculate the fluid flow and heat transfer solution with a realistic thermal boundary conditions. To address the ultimate thermal induced mechanical stress and reliability effects on the chip-packaged assembly due to the nonuniform chip power distribution, finite element model is employed for the sequential steady-state heat transfer and mechanical analysis. The results are then discussed and specifically compared with the solutions based on the uniform chip power conditions.

Performance projection and thermal management of high performance VLSI designs

The impact of chip self-heating induced temperature non-uniformity within the VLSI chip and its influence on the performance of the designs are described in this paper. To accurately model chip performance, both electrical and thermal analysis including chip packaging should be examined together. This paper describes a methodology that allows more accurate temperature calculation of the chip based on circuit power analysis, together with thermal analysis that studies the on chip temperature distribution in order to improve the accuracy of existing methods to account for on chip temperature gradients and perform an overall performance prediction and adjustment. A computational fluid dynamics analysis is used in this study to address non-uniform power distribution temperature calculation for high power integrated circuits. Examples are given and results discussed with highlighted conclusions.