Nan Zheng

Metamaterial sensor platforms for Terahertz DNA sensing

Three high-sensitivity metamaterial Terahertz DNA sensors based on resonance are proposed to distinguish DNA molecule with different refractive indices. Both numerical electromagnetic method and physical circuit model interpretation are employed to analyze proposed sensor structures. Design guideline based on intuitive physical circuit model is provided and verified through full-wave simulation.

Online Supervised Learning for Hardware-Based Multilayer Spiking Neural Networks Through the Modulation of Weight-Dependent Spike-Timing-Dependent Plasticity

In this paper, we propose an online learning algorithm for supervised learning in multilayer spiking neural networks (SNNs). It is found that the spike timings of neurons in an SNN can be exploited to estimate the gradients that are associated with each synapse. With the proposed method of estimating gradients, learning similar to the stochastic gradient descent process employed in a conventional artificial neural network (ANN) can be achieved. In addition to the conventional layer-by-layer backpropagation, a one-pass direct backpropagation is possible using the proposed learning algorithm. Two neural networks, with one and two hidden layers, are employed as examples to demonstrate the effectiveness of the proposed learning algorithms. Several techniques for more effective learning are discussed, including utilizing a random refractory period to avoid saturation of spikes, employing a quantization noise injection technique and pseudorandom initial conditions to decorrelate spike timings, in addition to leveraging the progressive precision in an SNN to reduce the inference latency and energy. Extensive parametric simulations are conducted to examine the aforementioned techniques. The learning algorithm is developed with the considerations of ease of hardware implementation and relative compatibility with the classic ANN-based learning. Therefore, the proposed algorithm not only enjoys the high energy efficiency and good scalability of an SNN in its specialized hardware but also benefits from the well-developed theory and techniques of conventional ANN-based learning. The Modified National Institute of Standards and Technology database benchmark test is conducted to verify the newly proposed learning algorithm. Classification correct rates of 97.2% and 97.8% are achieved for the one-hidden-layer and two-hidden-layer neural networks, respectively. Moreover, a brief discussion of the hardware implementations is presented for two mainstream architectures.

Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells

In energy-constrained applications, SRAM systems operating in the subthreshold region are often deployed to reduce power consumption. Subthreshold SRAM designs, however, confront numerous challenges, such as susceptibility to process variation and reduced ON–OFF current ratio. Statistical modeling of the variation in cell stability is critical in SRAM design, especially, for designs operating in the subthreshold region, where the process and temperature variations are the most pronounced. In this paper, statistical models for estimating the static noise margins (SNMs) of SRAM cells are built from the perspective of a shifted voltage transfer characteristic. Read (hold) SNM of a subthreshold 8T cell is analyzed. It is shown that the distribution of a single-sided read SNM is a weighted sum of several normal distributions instead of a regular Gaussian distribution. The proposed statistical model is verified with simulation results in 65-nm technology. Furthermore, to mitigate performance and yield degradation, an adaptive body biasing circuit is developed. It is demonstrated through simulation that, with a negligible area and power overhead, the proposed circuit achieves a 15% improvement in the worst case read SNM.

A low-power reconfigurable CMOS power amplifier for wireless sensor network applications

In this paper, a detailed methodology for designing a low-power high-efficiency power amplifier (PA) is presented. The trade-off between high efficiency and low output power is highlighted. An example is described to validate the proposed design method. Simulated peak efficiency up to 50.3% has been achieved with all components on-chip. Furthermore, a tunable power amplifier with efficiency enhanced at output power back-off region is proposed for more efficient operation.

A Scalable Low-Power Reconfigurable Accelerator for Action-Dependent Heuristic Dynamic Programming

Adaptive dynamic programming (ADP) is an effective algorithm that has been successfully deployed in various control tasks. For many emerging applications where power consumption is a major design consideration, the conventional way of implementing ADP as software executing on a general-purpose processor is not sufficient. This paper proposes a scalable and low-power hardware architecture for implementing one of the most popular forms of ADP called action-dependent heuristic dynamic programming. Different from most machine-learning accelerators that mainly focus on the inference operation, the proposed architecture is also designed for energy-efficient learning, considering the highly iterative and interactive nature of the ADP algorithm. In addition, a virtual update technique is proposed to speed up the computation and to improve the energy efficiency of the accelerators. Two design examples are presented to demonstrate the proposed algorithm and architecture. Compared with the software approach running on a general-purpose processor, the accelerator operating at 175 MHz achieves 270 times improvement in computational time while consuming merely 25 mW power. Furthermore, it is demonstrated that the proposed virtual update algorithm can effectively boost the energy efficiency of the accelerator. Improvements up to 1.64 times are observed in the benchmark tasks employed.

Hardware-Friendly Actor-Critic Reinforcement Learning Through Modulation of Spike-Timing-Dependent Plasticity

In this work, we propose a hardware-friendly reinforcement learning algorithm. The learning algorithm is based on an actor-critic structure implemented with spiking neural networks (SNNs). A biologically plausible and hardware-friendly spike-timing-dependent plasticity learning rule is formulated and employed in the training of SNNs. Several important aspects of applying the learning rule in a reinforcement learning context is studied, especially from the circuit designers’ point of view. Pitfalls of potential noise mixing and correlated spikes are identified and properly addressed. To feature a low-power learning architecture, techniques such as down-sampling data for certain learning blocks, injecting quantization noise as noisy residues in neurons, and proper memory partitioning are proposed. A 1-D state-value function learning problem and a 2-D maze walking problem are examined in this paper to illustrate effectiveness of the proposed algorithm and learning rules. A low-power hardware architecture is proposed and examples are implemented with Verilog. Hardware complexity of the proposed algorithm is analyzed, and potential solutions to breaking memory bottleneck when the size of the problem gets large is also discussed.

An Efficient Eligible Error Locator Polynomial Searching Algorithm and Hardware Architecture for One-Pass Chase Decoding of BCH Codes

In numerous memory and communication systems, Bose–Chaudhuri–Hocquenghem (BCH) codes are widely employed to enhance reliability. A one-pass Chase soft-decision decoding algorithm for BCH codes was previously proposed to achieve significant performance improvement over traditional hard-decision decoding while not increasing too much computational complexity. The bottleneck in conventional one-pass Chase decoding is the procedure of judging whether an obtained error locator polynomial is valid. In this brief, a novel algorithm that can efficiently verify eligibility of each generated error locator polynomial is proposed. The problem is first reformulated as a polynomial modulo problem, where repeated squaring can be employed for further simplification. In order to decrease the critical path delay and hardware complexity, an efficient polynomial division algorithm based on polynomial inversion is also proposed. In addition, a VLSI architecture for the proposed algorithm is presented. The implemented results show that the proposed eligibility checking algorithm reduces the gate counts to only 12% of a conventional polynomial selection algorithm without introducing any speed penalty. The projected area reduction achieved in a complete one-pass Chase decoder is approximately 75%. In addition, post-layout simulation shows that the proposed algorithm is 20 times more power efficient than the conventional method.

Ultra-Low Power Wireless Sensor Network SoC for Biosignal Sensing Application in 65nm CMOS

This paper presents an ultra-low power bio-signal sensing system on chip (SoC) fabricated in a 65nm CMOS technology. The proposed SoC processes a selected bio-signal (i.e. ECG, EMG, ECoG, Neural spike, and EEG), and packetizes it, and transmits through an RF transmitter by means of On-Off Keying (OOK) modulation scheme. In standby mode, the SoC consumes only 912 nW, while it consumes 6.1 uW when fully operating, which can be achieved by an aggressive duty-cycling (i.e. 0.2526%). With a standard Lithium-ion AA-sized battery, the proposed SoC can operate for more than 50 years. When equipped with energy harvesting (e.g. Temperature gradients), the proposed SoC can maintain operation permanently.