Yalcin Yilmaz

Image Processing by a Programmable Grid Comprising Quantum Dots and Memristors

Real-time vision systems require computationally intensive tasks which often benefit greatly from fast and accurate feature extractions. Resistive grid-based analog structures have been shown to perform these tasks with high accuracy and added advantages of compact area, noise immunity, and lower power consumption compared to their digital counterparts. However, these are static structures and can only perform one type of image processing task. In this paper, an analog programmable memristive grid-based architecture capable of performing various real-time image processing tasks such as edge and line detections is presented. The unit cell structure employs 3-D confined resonant tunneling diodes that are called quantum dots in this paper for signal amplification and latching, and these dots are interconnected between neighboring cells through nonvolatile continuously variable resistive elements that are more popularly known as memristors. A method to program memristive connections is introduced and verified through circuit simulations. Various diffusion characteristics, edge detection, and line detection tasks have been demonstrated through simulations using a 2-D array of the proposed cell structure and analytical models have been provided.

Multi-purpose neuro-architecture with memristors

An analog CMOS neuromorphic design utilizing spike timing dependent plasticity and memristor synapses is investigated for use in building a multi-purpose analog neuromorphic chip. In order to obtain a multi-purpose chip, a suitable architecture is established and several functions with the proposed architecture are shown. Using the IBM 90 nm CMOS9RF process, neurons are designed to interface with Verilog-A memristor synapse models to perform the XOR and Edge Detection functions.

Threshold Read Method for Multi-bit Memristive Crossbar Memory

Memristors have raised great interest in various logic and non-volatile memory applications. They are especially a good candidate for crossbar memory applications for their capability of being integrated in high densities and low switching power consumptions. In this paper we propose a novel read/write circuitry for memristive crossbar memories that enables reliable multilevel data storage in single cell while eliminating the use of reference resistors thus reducing the number of comparisons required. The proposed method can be used independent of the nonlinear characteristics of the memristive device and it can also be utilized by memory cells incorporating a memristor and series diodes.

Programmable quantum-dots memristor based architecture for image processing

An analog Cellular Neural Network (CNN) architecture employing quantum dots to realize various real time image processing applications such as edge and line detections and motion estimation is proposed. In order to obtain programmability to switch between applications, memristive connections between neighboring cells, and for signal amplification and locking resonant tunneling diodes (RTDs) are utilized. Simulations are carried out on a 2D array of the proposed cell structure to demonstrate edge detection and line detection tasks. This work also provides analytical models and simulation results to prove above mentioned real time image processing functionalities.

Nonvolatile Nanopipelining Logic Using Multiferroic Single-Domain Nanomagnets

Multiferroic single-domain nanomagnetics is a promising emerging nanotechnology poised to usher in ultralow energy nanomagnetic nonvolatile logic circuits in numerous medical applications, such as implants and prosthesis, where battery longevity is paramount. This paper evaluates the fundamental mode of signal propagation over ferromagnetically and antiferromagnetically coupled wires and interaction between the magnetic nanoparticles to perform nonvolatile logic functions, such the majority gate that sets its output to 1 when the majority of the inputs is 1. By taking advantage of magnetic nonvolatility, the paper demonstrates nanopipelining signal processing, data propagation performance, and functionality of basic building blocks. Our results indicate that effective nanopipeling can be achieved with clock periods approaching 9 ns and energy dissipation of 20 aJ per nanomagnet switch with the device sizes considered.

Towards EM based logic implementation using periodically corrugated metamaterial structures

In this paper, we have explored the feasibility of performing complex logic operations using periodically corrugated metamaterial waveguides. Selective manipulation of the free carrier concentration of the GaAs dielectric via external stimuli alters the filtering characteristics of the waveguide structure, enabling control over the propagation of terahertz carrier signal. We demonstrate that integration of individual control elements together can be utilized to implement AND and OR logic structures.

Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques

Different techniques of power savings in CMOS circuits have been investigated through the years. This work compares the asynchronous approach, the superthreshold approach, and the subthreshold approach in a 128 point FFT processor. The subthreshold design, made in TSMC 65 nm technology, utilizes a 4 kb SRAM with 8T unit cells. The sizing requirements for the 8T cell operated in subthreshold regime is explored as a function of static write margin. The subthreshold processor runs at 1 MHz with an energy consumption of 31 nJ/FFT. Subthreshold approach is seen to be the most energy efficient low power method of the three approaches.

A Drift-Tolerant Read/Write Scheme for Multilevel Memristor Memory

Memristor based crossbar memories are prime candidates to succeed the Flash as the mainstream nonvolatile memory due to their density, scalability, write endurance and capability of storing multibit per cell. In this paper, we present a memristor crossbar memory architecture that utilizes a reduced constraint read-monitored-write scheme. The proposed scheme supports multibit storage per cell and utilizes reduced hardware, aiming to decrease the feedback complexity and latency while still operating with CMOS compatible voltages. We additionally present a read technique that can successfully distinguish resistive states under the existence of resistance drift due to read/write disturbances in the array. We also provide derivations of analytical relations to set forth a design methodology in selecting peripheral device parameters.

Ultra-Low Power Wireless Sensor Network SoC for Biosignal Sensing Application in 65nm CMOS

This paper presents an ultra-low power bio-signal sensing system on chip (SoC) fabricated in a 65nm CMOS technology. The proposed SoC processes a selected bio-signal (i.e. ECG, EMG, ECoG, Neural spike, and EEG), and packetizes it, and transmits through an RF transmitter by means of On-Off Keying (OOK) modulation scheme. In standby mode, the SoC consumes only 912 nW, while it consumes 6.1 uW when fully operating, which can be achieved by an aggressive duty-cycling (i.e. 0.2526%). With a standard Lithium-ion AA-sized battery, the proposed SoC can operate for more than 50 years. When equipped with energy harvesting (e.g. Temperature gradients), the proposed SoC can maintain operation permanently.

Nanopipelining of NML using multiferroic single-domain nanomagnets

A recent technology, multiferroic single-domain nanomagnets are very promising for energy efficient nanomagnetic logic (NML) applications with benefits of ultra-low energy consumption and inherent non-volatility. In this paper we evaluate pipelined signal propagation in fundamental nanomagnetic logic elements using a four phase local clocking scheme. We demonstrate that low energy consuming operation is possible with this technology at single nanomagnet level reaching clock frequency of ∼100 MHz while still maintaining ultra-low energy consumption.