Nando Kaminski

Limitation of the short-circuit ruggedness of high-voltage IGBTs

In this paper, the destruction mechanism, which limits the short-circuit capability of high voltage IGBTs utilizing N-buffer structures will be described. The failure mechanism was studied using a combination of device simulations and experimental investigations of 3.3kV, 4.5kV and 6.5kV IGBTs. It was found that the limiting short-circuit failure in these IGBTs is caused by a current filamentation mechanism, which is associated to a distortion of the electric field triggered by a positive feedback effect between the carrier drift velocities and the electric field and the resulting potential distribution in the IGBT N-base.

The radial layout design concept for the Bi-mode insulated gate transistor

In this paper we present a new radial design concept for an optimized layout of anode shorts in the Bi-mode Insulating Gate Transistor (BiGT). The study shows that the arrangement of the n+-stripes plays a key role for the on-state characteristics of the BiGT. With the aid of 3D device simulations the visualization of the plasma distribution during the on-state conduction was obtained in a 0.25 × 4 mm2 large BiGT model area. The influence of the dimensioning and layout of the anode shorts was simulated and compared with measured on-state curves. A clear improvement of plasma distribution in the device when the stripes are arranged orthogonally (radially) to the pilot-IGBT boundary is observed in 3D simulations. Measurements confirm lower on-state losses as a result of better utilization of the device area.

Dynamics of incomplete ionized dopants and their impact on 4H/6H-SiC devices

The influence of incomplete ionization of dopants in 4H/6H-SiC on transient device behavior has been investigated numerically based on a self-consistent solution of the coupled system of Poissons equation, the continuity equations of electrons and holes, and balance equations for each donor or acceptor level. If the rise time of a reverse bias pulse is equal or smaller than the characteristic ionization time constant, a dynamically enlarged extension of depletion regions is obtained which can result in a dynamic punchthrough (PT) within back-to-back junction configurations. The respective time constants of nitrogen (N), aluminum (Al), and boron (B) mere measured as functions of temperature in 4H- and 6H-SiC using thermal admittance spectroscopy (AS) and deep level transient spectroscopy (DLTS). At room temperature, for instance, we obtained 60 ps/2 ps, 300 ps/10 ps, and 100 ns/100 ns for N (cubic site), Al, and B in 4H/6H-SiC, respectively. As the time constants of N and Al are small, transient incomplete ionization turns out to be negligible, at least within todays high-power device operation areas. Boron, on the other hand, influences significantly the dynamic device characteristics. In order to demonstrate the implications of these effects, numerical device simulations of a 6H-SiC double-implanted MOSFET and a 4H-SiC thyristor were performed. These simulations allow a detailed analysis of the transient device behavior and the onset of dynamic PT which strongly depends on temperature, structure parameters, and the external excitation.

Reverse conducting–IGBTs initial snapback phenomenon and its analytical modelling

Analytical models have been proposed to describe the onset current density for the initial snapback in the transistor on-state mode and in the blocking state of reverse conducting-insulated gate bipolar transistors (RC-IGBT) for the stripe and cylindrical designs of the anode shorts. In cylindrical case, there are two possible ways in designing the anode shorts and the authors have proposed an analytical model for each of them. The considered RC-IGBTs are vertical with soft punch-through type buffer designs. The analytical model has been evaluated with the aid of 2-D device simulations and measurements. The authors have investigated the initial snapback phenomenon for different voltage class devices at a given technology (anode and buffer profiles) and found out that the snapback voltage increases with the blocking capability but not the snapback current density. The authors have also observed that the initial snapback phenomenon is more pronounced at lower temperatures. From the analytical model as well as simulation and measurement results, the authors have found that for a given voltage class and technology, the p + -anode width is the only remaining design degree of freedom which determines the initial snapback. The adjustment of the on-state losses can then be done with the proportion of the n + -short region.

Acceleration of temperature humidity bias (THB) testing on IGBT modules by high bias levels

The temperature-humidity-bias (THB) test is the standard for accelerated stress testing with respect to corrosion and other humidity driven degradation mechanisms. Usually, 1000 hrs tests at 85 degree Celsius and 85 percent relative humidity (85/85) are used to predict up to 25 years of operation. With regard to the respective standards asking for limited self-heating, the bias was commonly limited to 80 V. Nevertheless, recent THB tests on 1.7 kV IGBT modules have shown that higher bias is a more severe test condition. Failure analysis confirmed corrosion of the Al chip-metallization as well as Cu-and Ag-dendrites as the relevant failure mechanisms. In order to determine the acceleration due to bias, 1.2 kV IGBT-modules were tested in THB at 65 percent and 90 percent of their nominal voltage Vnom, respectively. A characteristic degradation consisting of three phases has been identified. The 2nd phase seems to be determined by Al corrosion and a factor of about two has been estimated for the acceleration between the aforementioned test-voltages. Within the 3rd phase, the devices stabilized probably due to localized self-heating. Thus, this degradation mechanism is kind of self-limiting, but the higher leakage increases the risk of thermal runaway, i.e. catastrophic breakdown especially when biased close to Vnom.

A high voltage IGBT and diode chip set designed for the 2.8 kV DC link level with short circuit capability extending to the maximum blocking voltage

This paper presents the experimental characteristics of a high voltage IGBT and diode chip set designed for safe operation under hard switching conditions at the 2.8 kV DC link level. The fundamental goal of the design is a low cosmic ray induced failure rate for diodes as well as IGBTs at the DC link level. At the same time all the common requirements of low static and dynamic losses as well as wide SOA under turn-off, reverse recovery and short-circuit conditions are fulfilled. The blocking capability of these devices exceeds 4.5 kV by far.

Numerical simulation of implanted top-gate 6H–SiC JFET characteristics

Abstract A detailed numerical analysis of implanted top-gate 6H–SiC JFET structures was performed revealing the influence of a non-uniform channel doping profile. Based on structural parameters extracted from simulations of the device characteristics at various bias conditions and temperatures, we obtain channel mobility parameters close to Hall data for bulk epitaxial layers.

Stability of silicon carbide Schottky diodes against leakage current thermal runaway

Thermal stability is mandatory for the application of power semiconductor devices. Thermal runaway as a consequence of the feedback loop of increasing temperature and increasing leakage current is one risk, especially for Schottky-diodes featuring particular blocking characteristics. In this work the blocking characteristics of modern SiC-Schottky diodes including MPS and JBS types were measured and the stability was investigated by means of theoretical considerations as well as measurements. Even the worst devices are thermally stable far beyond their datasheet limits and have to be mistreated to show thermal runaway. For the time being thermal runaway is, thus, not a limiting factor for the thermal design of SiC-diodes. However, when going to the much higher operating temperatures promised by SiC the picture looks quite different again.

Optimisation of the reverse conducting IGBT for zero-voltage switching applications such as induction cookers

The reverse conducting-IGBT (RC-IGBT) is a well suited device for soft switching applications, that is, zero voltage switching (ZVS). However, standard RC-IGBTs are optimised for hard switching, which shows different switching waveforms compared with soft switching. In this study, the optimisation of the RC-IGBT is described for soft switching applications using the example of an induction cooker. The investigated induction cooker is implemented by using the single-ended quasi-resonant topology. Simulations show that main losses of the induction cooker occur in the induction coil and the RC-IGBT (power switch). The performance of the coil can be improved mainly by minimising the coil resistance. The IGBT-optimisation is based on the reduction of tail current in the soft switching mode. The IGBT thickness is decreased and the local lifetime is used to achieve lower tail current. A reduction of the overall losses by 30% is achievable. As a result, the cooling system of the IGBT can be smaller and cheaper.

Implementation and investigation of the dynamic active clamping for silicon carbide MOSFETs

Silicon carbide (SiC) devices are known for their fast switching transients. The combination of stray inductances in the load circuit and high di/dt values can lead to very high transient overvoltages. Therefore, the reduction of the stray inductance is one of the most important steps to utilise the full potential of SiC devices. However, in some applications the stray inductance cannot be reduced further and high overvoltages are unavoidable. Since protective circuitries like the Dynamic Voltage Rise Control (DVRC) and the “classical” Active Clamping (AC) do not sufficiently work for discrete SiC transistors, the interaction of a SiC MOSFET and the more promising Dynamic Active Clamping (DAC) is investigated to reduce overvoltages. As a consequence of parasitic elements, which affect the switching process, an improved version of the DAC is proposed. Beside the comparison of switching energies and overvoltages, the dependence on the MOSFET junction temperature is analysed to get a better understanding, how different operation conditions influence the efficiency of the DAC.